Bias Circuit Precharge Switching for Faster Start-Up Settling
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Solution Overview
Problem
Bias circuits in low power electronics, such as current references and current mirrors, experience long start-up periods due to settling of bias voltage levels, leading to inefficient power consumption and potential energy wastage, with existing techniques either disabling current flow or complicating circuit design.
Innovation Solution
A bias circuit design incorporating a switch array that charges transistors to supply voltage and ground during different modes of operation, enabling efficient charge-sharing to approximate final bias voltage quickly, thereby reducing start-up time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional techniques disable the bias circuit to cut current flow, then power consumption is reduced, but start-up time becomes excessively long due to charging node capacitances from zero
Solution Approach 1:
The patent applies preliminary action by pre-charging the gate voltages of the transistors to appropriate levels before the bias circuit is fully enabled. During the disable state, first transistors have their gates charged to a first voltage and second transistors have their gates charged to a second voltage, so that when the circuit transitions to the enable state, the bias voltages are already close to their target values, dramatically reducing the settling time required.
Solution Approach 2:
The patent segments the bias circuit into multiple transistor pairs (first transistors and second transistors) with independent gate voltage control. Each transistor pair can be independently charged to specific voltages through separate charging paths, allowing granular control over the bias voltage establishment process and enabling faster, more efficient start-up.
2Loss of time
If NMOS gate voltages are pulled to supply voltage and PMOS gate voltages to ground with separate transistors, then start-up time is reduced, but start-up current becomes many decades greater than final bias current, wasting energy
Solution Approach 1:
The patent changes the voltage parameters applied to transistor gates during start-up. Instead of applying full supply voltage or full ground potential, the circuit charges gates to specific intermediate voltages (first voltage for NMOS, second voltage for PMOS) that are tailored to establish the correct bias conditions. This precise parameter control enables fast start-up with minimal energy dissipation.
Solution Approach 2:
The patent introduces intermediary charging transistors that act as mediators between the power supply/ground and the bias circuit gates. These intermediary transistors control the charging process, allowing the gates to reach appropriate voltages through controlled current paths rather than direct connection to supply rails, thereby reducing energy wastage during the start-up transient.
3Loss of energy
If node voltages are made to float to preserve charge, then some energy is preserved, but voltages drift off mark and start-up length becomes highly dependent on duty cycle and temperature
Solution Approach 1:
The patent implements feedback by continuously monitoring the bias voltages and using the charged gate voltages of the first and second transistors to regulate and stabilize the output bias voltages. The pre-charged gates act as reference elements that provide feedback control, ensuring that the bias voltages settle to accurate, stable values regardless of duty cycle variations or temperature changes.
Solution Approach 2:
The patent changes the electrical state of the node voltages from floating to actively charged states. By applying specific voltages to the transistor gates through the switch array, the circuit establishes well-defined, stable voltage levels that are insensitive to external conditions such as duty cycle and temperature, thereby improving reliability while maintaining energy efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables faster start-up and reduced power consumption in low power electronics by efficiently utilizing existing capacitive charges to establish bias voltages, minimizing energy wastage and simplifying circuit design.
Implementation Method 1
Because the parasitic capacitance of the gates will be charged to a voltage representing full conduction
Implementation Method 2
utilizing existing capacitive charges to establish bias voltages
Data Source
AI summary
A bias circuit is provided. The bias circuit may include a first transistor forming an input node, a second transistor forming an output node, and a switch array disposed between the first transistor and the second transistor. The switch array may be configured to charge the first transistor to a supply voltage and the second transistor to a ground during a first mode of operation, and couple the first transistor to the second transistor to approximate a final bias voltage during a second mode of operation.