Bias Supply Circuit for Memory Cells with Multiple Gate Electrodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face challenges in achieving area efficiency due to the need for cascode transistors and sense amplifiers for each memory cell, which consume significant space and result in current variations across process, voltage, and temperature variations.
Innovation Solution
The implementation of a bias supply circuit that uses a bias memory cell of the same semiconductor conductivity type as the memory cell to generate a bias voltage, allowing for the omission of cascode transistors and sense amplifiers, and employing switches to selectively provide the bias voltage to multiple memory cells, thereby reducing area consumption and current variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cascode transistors and sense amplifiers are used for each memory cell, then reliability of memory operation is improved, but area consumption increases significantly
Solution Approach 1:
The patent merges the bias generation function from individual memory cell circuits into a shared bias supply circuit that serves multiple memory cells. The bias supply circuit generates a bias voltage that is distributed to control gates of multiple memory cells simultaneously, eliminating the need for separate cascode transistors and sense amplifiers at each memory cell location.
Solution Approach 2:
The bias supply circuit performs multiple functions: it generates the bias voltage, distributes it to multiple memory cells, and maintains stable operation across process, voltage, and temperature variations. This universal circuit replaces what would otherwise require dedicated components at each memory cell, achieving area efficiency while maintaining reliability.
2Manufacturing precision
If cascode transistors and sense amplifiers are implemented for each memory cell, then current control precision is improved, but device complexity increases
Solution Approach 1:
The patent extracts the current control function from individual memory cell circuits and consolidates it into the bias supply circuit. By taking out the bias generation functionality and placing it in a dedicated circuit, the design achieves current control precision without requiring complex structures at each memory cell location.
3Area of stationary object
If bias supply circuit with bias memory cell is used, then area efficiency is improved, but current variations across PVT conditions worsen
Solution Approach 1:
The bias supply circuit incorporates feedback mechanisms that monitor and adjust the bias voltage to maintain stable operation across process, voltage, and temperature variations. This feedback ensures that current variations are compensated, maintaining reliability while achieving area efficiency through the shared bias generation approach.
Data Source
AI summary
Disclosed herein are related to a memory device including a memory cell and a bias supply circuit providing a bias voltage to the memory cell. In one aspect, the bias supply circuit includes a bias memory cell coupled to the memory cell, where the bias memory cell and the memory cell may be of a same semiconductor conductivity type. The memory cell may include at least two gate electrodes, and the bias memory cell may include at least two gate electrodes. In one configuration, the bias memory cell includes a drain electrode coupled to one of the at least two gate electrodes of the bias memory cell. In this configuration, the bias voltage provided to the memory cell can be controlled by regulating or controlling current provided to the drain electrode of the bias memory cell.