Biasing Unselected Word Lines to Reduce Bit Line Leakage
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Solution Overview
Problem
Bit line leakage current in non-volatile memory systems affects sensing speed, particularly in memory with long bit lines or reading bits with low cell current, due to current leakage through unselected, strongly programmed memory cells.
Innovation Solution
Biasing an unselected program word line to a bias voltage during read operations or at all times, or biasing an unselected memory cell to a negative bias voltage, to reduce bit line leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If read operations are performed on non-volatile memory with long bit lines or low cell current, then memory access is enabled, but bit line leakage current increases causing reduced sensing speed
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a specific voltage level before the read operation begins. This pre-charging action prepares the bit line in advance to compensate for the leakage current that will occur during the read operation, ensuring that the sensing speed is not degraded by the leakage.
Solution Approach 2:
The patent changes the voltage parameter of the bit line dynamically. During read operations, the bit line voltage is adjusted to account for leakage current effects. This parameter change allows the system to maintain accurate sensing despite the presence of leakage current through unselected memory cells.
2Quantity of substance
If unselected memory cells are strongly programmed, then data storage capacity is improved, but leakage current through these cells increases during read operations
Solution Approach 1:
The patent applies local quality by differentiating the treatment of selected and unselected memory cells. Unselected memory cells are subjected to a different voltage condition (pre-charging) compared to selected cells during read operations. This local differentiation allows strongly programmed unselected cells to maintain their data storage function while minimizing their harmful leakage effect on the read operation.
Data Source
AI summary
In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations.