Bi-directional BJT ESD Protection Structure

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Solution Overview

Problem

High voltage devices face challenges in electrostatic discharge (ESD) protection due to low on-state resistance, high breakdown voltage, and low holding voltage characteristics, which can lead to physical destruction and latch-up issues during ESD events, especially in motor driver circuits where parasitic diodes can cause irregular operation.

Innovation Solution

A bi-directional bipolar junction transistor (BJT) is developed using a modified BCD process with an epitaxial structure, incorporating a p-type substrate, N+ doped buried layer, N-type well region, and P-type well regions with field oxide films and plates, allowing for bi-directional ESD protection without increasing device size or introducing additional masks, and enabling adjustable breakdown and trigger voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the surface or lateral rules are increased to improve ESD performance, then ESD protection capability is improved, but device size increases

Engineering Contradiction:
ImproveESD protection capabilityVSAvoiddevice size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent modifies the BJT structure by changing doping parameters and junction characteristics to achieve lower breakdown voltage and trigger voltage. This allows the device to provide ESD protection without requiring increased surface or lateral dimensions, thus maintaining small device size while improving ESD performance.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces a vertical junction structure with multiple doped regions (N+, P+, N-) stacked in the vertical dimension. This three-dimensional configuration enables ESD protection functionality without increasing the lateral surface area, effectively moving the solution from a two-dimensional to three-dimensional approach.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If low on-state resistance is used to improve device performance, then current conduction is improved, but ESD current concentration increases

Engineering Contradiction:
Improvecurrent conduction efficiencyVSAvoidESD current concentration
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by creating regions with different doping concentrations and resistance characteristics within the BJT structure. The collector and emitter regions have optimized doping profiles that provide low on-state resistance for normal current conduction, while the base region and junction interfaces are designed to distribute ESD current more evenly, preventing concentration at specific points.

Inventive Principle:
Principle #3Local quality

3Reliability

If additional masks and processes are used to create larger diodes for ESD protection, then ESD performance is improved, but manufacturing complexity increases

Engineering Contradiction:
ImproveESD protectionVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the BJT structure multi-functional by designing it to provide both normal transistor operation and ESD protection functions through its inherent BJT physics. The same NPN and PNP transistor structures that enable switching and amplification functions also provide the voltage breakdown characteristics needed for ESD protection, eliminating the need for separate ESD protection structures and reducing manufacturing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8963253B2Bi-directional bipolar junction transistor for high voltage electrostatic discharge protection
Publication Date: 2015.02.24 MACRONIX INTERNATIONAL CO LTD
  • US8963253B2 patent drawing
  • US8963253B2 patent drawing
  • US8963253B2 patent drawing

AI summary

A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.