Bidirectional Level-Shifting Circuit for Open-Drain Deadlock Prevention
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Solution Overview
Problem
Existing bidirectional I/O circuits face challenges in interfacing modern integrated circuits with legacy interfaces having different signal levels, leading to capacitive load issues and potential deadlock situations due to inability to distinguish between externally and internally driven signals on open-drain buses.
Innovation Solution
A bidirectional level-shifting device with comparator and limiter circuits that adjust driving voltages based on reference voltages, allowing for accurate distinction between externally and internally driven signals, and limiting output to prevent deadlock situations across a wide range of signaling levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If passive level-shifting is used to interface modern IC with legacy interfaces, then signal level compatibility is achieved, but capacitive load increases and signal slewing occurs
Solution Approach 1:
The patent introduces an active buffer circuit as an intermediary between the modern IC and legacy interface. This buffer actively drives the signal while providing ESD protection and decoupling the capacitive load, thereby maintaining signal integrity while achieving voltage level compatibility between different domains (e.g., 1.8V IC to 5V legacy interface).
Solution Approach 2:
The patent dynamically adjusts the output impedance and driving strength of the buffer circuit based on the detected voltage level and load conditions. By changing the operating parameters of the buffer (such as enabling/disabling ESD protection diodes, adjusting drive strength), it optimizes signal quality across different voltage domains and prevents signal slewing.
2Reliability
If active buffer implementation is used for level-shifting, then load capacitance is decoupled and ESD protection is provided, but deadlock situation may occur due to inability to distinguish external and internal signals
Solution Approach 1:
The patent implements a feedback mechanism where the buffer circuit continuously monitors its own output state and compares it with the input signal. By detecting whether a low signal state is caused by an external driver or by its own internal driving, the buffer can prevent false triggering and avoid deadlock situations on open-drain buses. The feedback loop enables the circuit to distinguish between externally driven signals and internally generated signals.
3Adaptability or versatility
If open-drain bus is used for bidirectional communication, then flexibility is improved, but deadlock situation occurs when external and internal signals cannot be distinguished
Solution Approach 1:
The patent enables the buffer circuit to preemptively detect the state of the external bus before attempting to drive internally generated signals. By checking whether an external driver is already present on the bus, the circuit prevents conflicting drive conditions that would cause deadlock. This preliminary detection action ensures stable open-drain bus operation while maintaining bidirectional communication flexibility.
Data Source
AI summary
Level-shifting devices and methods allow signals to be passed between input/output (I/O) ports. One such device comprises a first output driver that drives a first I/O port in response to a first control signal. A second output driver drives a second I/O port in response to a second control signal. A first comparator circuit, responsive to a first reference voltage and a voltage at the first I/O port, generates the second control signal. A limiter circuit limits driving of the second I/O port, by the second driver, to a limiting voltage that responsive to a the second I/O port over a first range of signaling voltages, and constrained to a set value over a second range. A voltage reference generating circuit generates a second reference voltage. A second comparator circuit generates the first control signal in response to the second reference voltage and the second I/O port.