Bi-directional Resistive Memory Cell for High-Speed Non-Volatile Storage
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Solution Overview
Problem
Conventional resistive memory devices exhibit slow read and write performance, making them unsuitable for replacing SRAM in high-performance systems, and are difficult to produce reliably in one transistor/one resistive element or one diode/one resistive element configurations.
Innovation Solution
Implementing bi-directional resistive elements in a four transistor dynamic random access memory (DRAM) or six transistor SRAM cell configuration, allowing for read operations in less than five nanoseconds and write operations in less than ten nanoseconds, with data stored non-volatilely using conventional techniques and restored upon power-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If one transistor/one resistive element or one diode/one resistive element memory cell configuration is used, then cell area is minimized, but read and write performance becomes slow (approximately 30 nanoseconds or more per operation)
Solution Approach 1:
The patent divides the memory cell into multiple transistors (four or six transistors) rather than using a single transistor, creating a more complex but faster-cycling cell structure that can achieve read/write operations in a few clock cycles comparable to SRAM
Solution Approach 2:
The patent combines multiple transistors with resistive elements in an integrated memory cell structure, merging the advantages of resistive memory (non-volatility, compact area) with the speed characteristics of transistor-based SRAM architectures
2Area of moving object
If one transistor/one resistive element or one diode/one resistive element memory cell configuration is used, then cell area is minimized, but manufacturing reliability becomes difficult to achieve
Solution Approach 1:
The patent segments the memory cell into multiple transistors and resistive elements, distributing the functional requirements across multiple components rather than relying on a single critical transistor-resistive element pair, thereby improving manufacturing yield and reliability
Solution Approach 2:
The patent assigns different functional roles to different transistors within the cell (e.g., access transistors, drive transistors, sense transistors), allowing each component to be optimized for its specific function and improving overall cell reliability
3Stability of the object's composition
If conventional resistive memory devices are used, then non-volatile storage is achieved, but read and write speeds are slow making them unsuitable for replacing SRAM in high-performance systems
Solution Approach 1:
The patent merges resistive memory elements (providing non-volatility) with multi-transistor SRAM-like circuitry (providing high speed), creating a hybrid memory cell that achieves both non-volatile storage and SRAM-comparable read/write speeds of a few clock cycles
Solution Approach 2:
The patent employs dynamic operation modes with multiple transistors that can rapidly switch between states, enabling fast read and write operations while maintaining the non-volatile data retention capability of resistive elements
Data Source
AI summary
A memory cell includes a first storage node and a second storage node that is complementary to the first storage node. A first bidirectional resistive memory element (BRME) includes a first terminal, a second BRME includes a first terminal. A first access transistor couples the first storage node to a first bit line. A second access transistor couples the second storage node to a second bit line. A third transistor couples the first terminal of the first BRME to the second bit line. A fourth transistor couples the first terminal of the second BRME to the first bit line.