Digital Storage TRIZ Cases

A cross-coupled inverter latch cuts transistor count and wiring while preserving data retention plus input and output bus transfer.

Single flux quantum pulses set and read a storage loop in a Josephson D-gate memory circuit, enabling fast, low-power digital state retention.

Dynamic delay and feedback alignment keep external memory boot-data capture stable across on-chip and off-chip PVT variation.

Splitting commands into even and odd half-frequency paths gives flip-flops more logic time without raising the external clock rate.

CES elements stabilize sense amplifier impedance despite temperature and process variation, reducing read offset and bit-line errors.

A dual-mode control circuit reads and writes storage circuits during runtime, enabling fault injection and debugging without stopping execution.

Uniform pulse-width control and glitch filtering keep memory refresh stable at low tCK, preventing abnormal internal signals and data loss.

A three-port FPGA RAM block adds dual read ports and a write port to build register files with flexible timing and lower resource use.

Bit-period adjustment and parallel signal selection remove ISI while recovering sampling margin and lowering power versus DFE-based equalization.

Cycle-by-cycle switching lets logic elements share channels dynamically, cutting wiring demand while sustaining fast parallel data processing.

Superconducting spin-polarized current switching extends spin signal range while improving ON/OFF ratio and reducing Joule heating.

Ovonic threshold switching and bias-voltage control generate precise program current in compact PCRAM write drivers for fast non-volatile storage.

Hierarchical data lines and dual-mode memory cells cut leakage, improve read margin, and avoid large level shifters in programmable ICs.

Delay-based quadrature clock generation avoids divider frequency loss while cutting initialization time and power with phase error held within ±8.1 ps.

A combined latch and level shifter cuts leakage paths in dual-rail SRAM while reducing area and gate delay from separate circuits.

Stored line charge is reused as drive voltage, cutting I/O power consumption while sustaining high-speed data transmission.

Unused LUTRAM cells are reassigned as CRAM with gated writes and masked reads to save FPGA area and cut leakage power.

Push-pull buffers replace resistor-loaded logic stages to reduce RC nonlinearity and improve phase interpolator linearity with lower area and power.

An intermediate signal circuit helps a consumable chip distinguish read and write intents from current or voltage source signals.

Staggered latch clock phases across adjacent IC channels prevent cross-talk distortion while avoiding shielding, encoding, and added circuit cost.

Configurable interconnects let soft logic bypass or augment hard logic blocks, improving flexibility without giving up speed or low power.

Single flux quantum pulses and a storage loop enable cryogenic memory write-read operation with high speed and low power beyond CMOS limits.

CES elements stabilize sense amplifier input impedance, reducing offset voltage and read errors from temperature and process variation.

A superconducting spin-valve circuit preserves spin signals over compact paths while raising ON/OFF ratio and minimizing Joule dissipation.

Redundant input terminals and selectors reroute signals around defective pins, preserving bandwidth while reducing noise and current use.

Segmented original drive signals let a piezoelectric inkjet driver maintain high pseudo-resolution while cutting switch complexity and power use.

Using correlated electron switching, this latch retains data through power loss without redundant retention circuits or extra power supplies.

Both sense amplifier outputs actively drive primary and secondary latch paths to cut memory access time and simplify stacked gate logic.

Using both clock edges, configurable storage and processing blocks raise PLD throughput while reducing the number of specialized blocks.

A delayed input and its complement create automatic high-impedance timing, cutting enable circuitry, power use, and substrate area.

Dynamic switch control stores latched data in non-volatile memory before power loss, preserving state without continuous power.

Internal per-pin VREF correction tracks voltage-temperature drift without using DQ bus calibration, cutting latency and power.

A control circuit enables fast read/write access to storage circuits during execution for debug, fault injection, and state monitoring.

A segmented amplifier with inverter timing and discharge feedback preserves DQS and BDQS signal crossing in high-speed memory operation.

Switching between rising and falling clock edges reduces skew and avoids trial-and-error delay tuning during chip layout.

Cross-coupled current mirrors and split P/N amplifier paths speed memory interface response while lowering chip power use.

Bit requests are sorted by address unit and offset to speed FPGA signal reads and writes without changing the active configuration.

Dedicated address registers enable parallel CRAM frame programming, cutting FPGA configuration time and speeding boot-up for larger devices.

A tracking circuit resets the pulse generator from chip-domain voltage, preserving memory-clock noise margin across large voltage differences.

Switchable resistor branches let rewritable non-volatile memory mimic resistance-coded chip signals for printer consumables.

CRC-based soft error detection uses sensitivity map data to identify critical logic regions and avoid unnecessary reconfiguration.

A clock detector and SR latch shut down the LPDDR2 clock input buffer during stable periods, then re-enable it on toggling to cut power.

An isolation buffer and delayed reset latch clock edges cleanly, reducing timing marginalities and slew-rate errors in internal clock generation.

On-die STT-MRAM stores FPGA and CPLA configuration data to cut leakage power, remove external memory, and enable instant startup.

Comparator-guided address matching and data selection keep pipelined embedded memory reads coherent with concurrent writes.

A counter, delay, and combination circuit converts external DDR strobes into stable internal SDR signals with better timing margins.

Calibrates DDR data, strobe, and clock delays to correct duty cycle distortion and find valid timing windows across memory ranks.

Memristive logic cells merge storage and Boolean computation in one array, cutting CMOS area demands and lowering power use.

Selective latch control compares differential signal phases before preambles to block DC current, preserve duty alignment, and cut power use.

A phase-change magnetic film uses Joule heating and magnetic switching to combine non-volatile storage with OR, NOR, AND, and NAND logic.

Suppression circuitry selectively resets DFE buffers based on write operation intervals, resolving the trade-off between throughput and measurement precision.

Segmenting the write current path reduces power dissipation and aging by decoupling high-current writing from sensitive reading operations.

A semiconductor storage device manages sense amplifier blocks to optimize burst access speed across multiple banks.

A control circuit in magnetoresistive memory selectively switches write modes to reduce energy usage during data operations.

A 2-stage address decoder circuit uses NOR and NAND gates to process input bits efficiently.

Data bus inversion encoding reduces power consumption and switching noises in 3D memory by limiting simultaneous bit transitions through through substrate vias.

Dynamic reference bias level adjustment minimizes fail bits caused by resistance dispersion variations in variable resistance memory devices.

A bi-directional resistive memory cell uses multiple transistors to store data non-volatily.

A spin-transfer torque memory cell uses dual read currents to generate distinct bit line voltages for state determination.