Semiconductor Storage Device Burst Access Control
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Solution Overview
Problem
Existing semiconductor storage devices face limitations in achieving high-speed burst access, particularly when the start address is near the end of the simultaneous access unit, leading to delays and reduced operating speed in non-wrapping modes.
Innovation Solution
A semiconductor storage device with multiple banks and shared sense amplifier blocks, which selects and controls sense amplifier blocks to access different or the same banks based on assigned addresses, using a judging section to determine if the block address is the largest value, thereby optimizing access to minimize delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the non-wrapping mode is used with start address near the end of simultaneous access unit, then the burst access can proceed sequentially through all banks, but delays occur and operating speed decreases
Solution Approach 1:
The patent dynamically adjusts the bank selection strategy based on the block address value. When the block address is not the largest value, sense amplifier blocks access the same bank; when the block address is the largest value, they access different banks. This dynamic adaptation eliminates delays caused by fixed access patterns near the end of simultaneous access units.
Solution Approach 2:
The patent changes the bank address parameter based on the judging result of the block address. By modifying the bank address assignment strategy according to the specific address value, the system optimizes access timing and eliminates delays that would otherwise occur in non-wrapping mode with end-near start addresses.
2Speed
If multiple sense amplifier blocks are operated simultaneously to access different banks, then high-speed burst access is achieved, but the control complexity increases
Solution Approach 1:
The patent segments the control logic into distinct functional sections: a selecting section that divides sense amplifier blocks based on bank address, and a judging section that determines the largest block address value. This segmentation simplifies the overall control complexity by breaking down the decision-making process into manageable, independent modules.
Solution Approach 2:
The patent introduces an intermediary judging section that acts as a mediator between the address input and the bank selection process. This judging section evaluates whether the block address is the largest value and provides control signals to the selecting section, thereby simplifying the control logic while enabling high-speed simultaneous access to multiple banks.
3Productivity
If the start address is near the end of simultaneous access unit in non-wrapping mode, then sequential access through all banks is possible, but power consumption increases due to unnecessary sense amplifier operations
Solution Approach 1:
The patent applies partial action by selectively activating sense amplifier blocks based on the block address value. When the block address is not the largest value, only necessary sense amplifier blocks are activated to access the same bank, avoiding excessive power consumption from activating all sense amplifier blocks unnecessarily.
Data Source
AI summary
In writing and reading data at a semiconductor storage device, control is carried out such that, at a time of a burst mode, in a case in which a value of a block address which is, from addresses assigned to a region of an internal address, an address for selecting a sense amplifier block from plural sense amplifier blocks, is a largest value, a first sense amplifier block and a second sense amplifier block are made to access different banks, and, in case in which the value of the block address is not the largest value, the first sense amplifier block and the second sense amplifier block are made to access a same bank of plural banks.