Pulse Latch Reset Tracking Across High Differential Voltage Domains
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Solution Overview
Problem
Pulse latch circuits in memory devices face challenges in maintaining signal integrity and noise margin due to large voltage level differences between chip and memory domains, leading to poor clock slope and potential errors in memory operations.
Innovation Solution
A pulse generator and tracking circuit configuration that receives a clock signal in a first power domain and initiates a second clock signal in a second power domain, with a reset signal generated based on the voltage level of the first power domain to reset the pulse generator, utilizing nMOS and pMOS transistors and NOR gates to manage clock signals across different voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a pulse latch circuit operates across large voltage level differences between chip and memory domains, then clock signal transfer between domains is enabled, but noise margin and signal integrity deteriorate
Solution Approach 1:
A tracking circuit is introduced as an intermediary between the chip domain and memory domain clock circuits. This tracking circuit monitors the chip domain voltage level and generates a reset signal that adapts to the voltage differences, thereby maintaining signal integrity and noise margin while enabling operation across different voltage domains
Solution Approach 2:
The tracking circuit implements a feedback mechanism by continuously monitoring the chip domain voltage level and using this information to generate an appropriate reset signal for the memory domain clock circuit. This feedback loop ensures that the clock circuit adapts to varying voltage conditions, maintaining reliable operation across different voltage domains
2Productivity
If external clock signals are used to drive memory operations, then memory device operation is enabled, but the system becomes vulnerable to external noise and voltage variations
Solution Approach 1:
The memory device's clock circuit is designed to be self-sufficient by generating its own internal clock signals based on monitoring of the chip domain voltage. The tracking circuit enables the memory domain clock circuit to autonomously adapt to voltage variations and generate stable clock signals without being directly driven by external clock sources, thereby reducing susceptibility to external noise while maintaining high-speed operation
Data Source
AI summary
A method and an apparatus for generating an internal memory clock are provided. The apparatus includes a pulse generator configured to receive a first clock signal in a first power domain and initiate a second clock signal in a second power domain in response to the first clock signal. The first power domain provides a first voltage for logic operations and the second power domain provides a second voltage for memory operations. The apparatus includes a tracking circuit configured to generate a reset signal based on a voltage level of the first power domain. The reset signal may be configured to reset the pulse generator in the first power domain. The apparatus may further include a latch configured to receive the second clock signal in the second power domain.