Uni-stage Delay Speculative Address Decoder for Memory Arrays

Solution Overview

Problem

Larger memory arrays require more address decoder logic, leading to bottlenecks in memory access speed, increased circuit area, and power consumption, as existing address decoders face challenges in efficiently handling larger address spaces.

Innovation Solution

A 2-stage address decoder circuit design that uses NOR and NAND gates with inverters, where each decoder circuit receives 2n input bits including address and complement signals, allowing for efficient decoding across any size address space with minimal delay and resource usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If larger memory arrays are implemented to increase memory space, then the address space increases, but the amount of address decoder logic increases leading to bottlenecks in memory access speed

Engineering Contradiction:

Improvememory spaceVSAvoidmemory access speed

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

The address decoder is divided into multiple hierarchical levels: a first level decoder that decodes a first portion of the address, a second level decoder that decodes a second portion of the address, and a third level decoder that decodes a third portion of the address. This segmentation distributes the decoding workload across multiple specialized units, preventing any single decoder from becoming a bottleneck while maintaining the ability to address large memory spaces.

Inventive Principle:

Principle #1Segmentation

2Quantity of substance

If larger memory arrays are implemented to increase memory space, then the address space increases, but the circuit area and power consumption increase

Engineering Contradiction:

Improvememory spaceVSAvoidcircuit area

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The address decoder is divided into multiple hierarchical levels: a first level decoder that decodes a first portion of the address, a second level decoder that decodes a second portion of the address, and a third level decoder that decodes a third portion of the address. This segmentation distributes the decoding workload across multiple specialized units, preventing any single decoder from becoming a bottleneck while maintaining the ability to address large memory spaces.

Inventive Principle:

Principle #1Segmentation

3Quantity of substance

If more address decoder logic is added to handle larger address spaces, then the address space capacity increases, but the memory access speed decreases due to bottlenecks

Engineering Contradiction:

Improveaddress space capacityVSAvoidmemory access speed

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The address decoder is divided into multiple hierarchical levels: a first level decoder that decodes a first portion of the address, a second level decoder that decodes a second portion of the address, and a third level decoder that decodes a third portion of the address. This segmentation distributes the decoding workload across multiple specialized units, preventing any single decoder from becoming a bottleneck while maintaining the ability to address large memory spaces.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The address decoding process is initiated in advance by pre-charging the word lines before the full address is available. The decoders begin their operation early based on available address portions, and the word lines are pre-charged to reduce the time required for the actual decoding and activation, thereby maintaining fast access speeds even with large address spaces.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentEP1958204B1Uni-stage delay speculative address decoder

Publication Date: 2013.12.25 ADVANCED MICRO DEVICES INC

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AI summary

An address decoder. The address decoder includes a plurality of decoder circuits. Each decoder circuit includes a first stage including a first logic circuit having n-1 inputs, the n-1 inputs being a subset of n inputs conveyed to each decoder circuit. Each decoder circuit further includes a second stage having a second and third logic circuits. Both the second and third logic circuits receive an output provided by the first logic circuit. The second logic circuit also receives the other one of the n bits, while the third logic circuit receives its complement. The second and third logic circuits provide second and third outputs, respectively. The address decoder is configured to assert one of a plurality of address selection outputs by asserting one of the second or third outputs of one of the decoder circuits, while de-asserting both the second or third outputs of the other decoder circuits.