Configurable PLD Blocks With Double-Data-Rate Interconnect
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Solution Overview
Problem
Programmable logic devices (PLDs) often underutilize specialized blocks due to their clock frequencies being lower than their designed capabilities, leading to unexploited performance and increased implementation costs due to the need for more blocks to operate at single data rates.
Innovation Solution
Implementing configurable storage and processing blocks with interconnect circuitry that allows operation at double data rates, enabling data processing during both rising and falling clock edges, and using data rate selector circuits to aggregate or separate signals accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If specialized blocks operate at single data rates, then device complexity is reduced, but productivity is decreased
Solution Approach 1:
The specialized blocks are configured to dynamically operate at different data rates (single or double) based on timing requirements. The interconnect circuitry adapts its operation mode to match the clock frequency capabilities of connected blocks, allowing the system to optimize throughput without increasing the number of blocks.
Solution Approach 2:
The system changes the operational parameter of data rate from fixed single data rate to variable double data rate. By adjusting the timing of signal transmission and registration to utilize both rising and falling clock edges, the effective throughput doubles without adding more specialized blocks, thus resolving the contradiction between complexity and productivity.
2Productivity
If specialized blocks are designed for higher clock frequencies, then productivity is improved, but device complexity increases
Solution Approach 1:
The interconnect circuitry is designed with multi-functionality to handle both single data rate and double data rate operations. The same physical infrastructure supports different operational modes, allowing specialized blocks to operate at higher clock frequencies without requiring separate dedicated interconnect paths for each data rate mode.
Solution Approach 2:
The interconnect circuitry acts as an intermediary that mediates between specialized blocks operating at different clock frequencies and data rates. It provides timing synchronization and signal conditioning to enable high-frequency operation while maintaining compatibility with various block configurations, thus managing complexity through a standardized interface layer.
3Reliability
If more specialized blocks are used to operate at single data rates, then reliability is improved, but loss of substance increases
Solution Approach 1:
The double data rate operation enables continuous useful action by utilizing both rising and falling clock edges for data transmission. This doubles the effective throughput of each specialized block, reducing the need for additional blocks while maintaining operational reliability through consistent timing protocols and synchronized registration.
Data Source
AI summary
Integrated circuits such as application specific circuits or programmable logic devices may include specialized blocks such as configurable storage blocks and configurable processing blocks. Such specialized blocks may be controlled by clock signals and operated at single data rate or at double data rate. For instance, configurable storage blocks may be configured to use a double data rate communications scheme or a single data rate communication scheme to communicate data with other blocks. Configurable processing blocks may be configured to process data at a double data rate or a single data rate. Furthermore, configurable processing blocks that include accumulator circuitry may be configured to perform one accumulation at a single data rate or at a double data rate. Such configurable processing blocks may also be configured to perform two accumulations at a single data rate.