ISI Compensation Circuit Using Bit-Period Adjustment and Signal Selection
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Solution Overview
Problem
Conventional decision feedback equalizers (DFE) for intersymbol interference (ISI) compensation face challenges in accurately selecting filter coefficients, leading to reduced sampling margin and increased power consumption, especially as data rates increase and signals become more susceptible to noise and distortion.
Innovation Solution
An ISI compensation circuit that adjusts bit periods of input data signals using a combination of AND and OR operations, sampling circuits, and decision generation mechanisms to generate compensated values, allowing for effective ISI removal without requiring accurate coefficient selection or significant power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional decision feedback equalizer (DFE) is used to compensate for intersymbol interference, then ISI compensation is achieved, but accurate selection of FIR filter coefficients is required which increases device complexity and may reduce sampling margin
Solution Approach 1:
The patent extracts and removes the complex FIR filter coefficient selection mechanism from the equalization process. Instead of using a conventional DFE with adjustable coefficients, the invention uses a simplified structure that processes signals through parallel paths with fixed operations, eliminating the need for complex coefficient selection while maintaining ISI compensation effectiveness
Solution Approach 2:
The patent segments the signal processing into multiple parallel paths (first and second adjusted signals) that are processed independently and then combined. This segmentation allows each path to use simple fixed operations rather than requiring complex coordinated coefficient adjustments, reducing overall system complexity while achieving effective equalization
2Reliability
If a conventional DFE with accurate coefficients is used, then ISI compensation is achieved, but power consumption increases significantly
Solution Approach 1:
The patent employs simple, low-power logic operations (AND, OR) that can be implemented with basic digital circuits rather than complex adaptive filters. These operations consume significantly less power while achieving the necessary signal conditioning, effectively replacing high-power DFE components with lower-power alternatives that perform the essential function
3Reliability
If a conventional DFE is used for ISI compensation, then signal quality is improved, but the circuit requires more area
Solution Approach 1:
The patent merges multiple signal processing functions into a compact structure where parallel paths share common resources and logic. The first and second adjusted signals are generated through shared logic operations and combined through simple selection, reducing the total circuit area compared to a conventional DFE that would require separate filter banks, coefficient memory, and control logic for each function
Data Source
AI summary
An intersymbol interference (ISI) compensation circuit includes a data input for receiving an input data signal including a plurality of bits. An adjustment circuit is configured to adjust bit periods of the bits to generate a first adjusted signal and a second adjusted signal. A sampling circuit is configured to generate a first sample signal by sampling the first adjusted signal, and generate a second sample signal by sampling the second adjusted signal. A decision generation circuit is configured to provide a first decision for a first bit. The first decision provides a chosen adjusted signal that is one of the first and second adjusted signals. A selection circuit is configured to determine a compensated value of the first bit based on a chosen sample signal that is one of the first and second sample signals. The chosen sample signal is generated by sampling the chosen adjusted signal.