Memory Refresh Pulse Width Control Under Low tCK
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Solution Overview
Problem
Semiconductor memory devices face data loss due to charge leakage in cell capacitors, which is exacerbated by abnormal pulse widths of internal signals caused by low clock cycle tCK during refresh operations, disrupting normal device operation.
Innovation Solution
A semiconductor memory device with a high frequency signal control unit to remove noise and glitches, a pulse width control unit to adjust or maintain the pulse width of command address signals, and a refresh operation control unit to generate appropriate row addresses for controlled refresh operations, ensuring normal operation even at low clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a low clock cycle tCK is used during refresh operations to simplify the process and increase test time reduction efficiency, then test efficiency is improved, but the pulse width of internal signals becomes abnormally wide which interrupts normal internal operation
Solution Approach 1:
A pulse width control unit is introduced as an intermediary component between the external low-frequency clock signal and the internal refresh operation circuits. This unit adjusts the pulse width of command address signals to maintain appropriate durations despite the low clock cycle, thereby mediating between the test efficiency requirement and the normal operation requirement without allowing the abnormal wide pulse widths to reach internal circuits
Solution Approach 2:
The pulse width control unit dynamically adjusts the pulse width parameter of command address signals based on the clock cycle tCK. When a low clock cycle is detected, the unit extends the pulse width to compensate for the slower timing, ensuring that internal signals maintain their required pulse width characteristics for proper operation while still operating under the low-frequency external clock
2Reliability
If the pulse width of command address signals is extended to compensate for low clock cycle, then normal operation is maintained, but noise and glitches in the signal become more problematic
Solution Approach 1:
The high frequency signal control unit performs preliminary filtering and noise removal on command address signals before they are processed by the pulse width control unit. By cleaning the signals in advance, the system prevents noise and glitches from being amplified or propagated during the pulse width adjustment process, thus maintaining signal integrity while still achieving the required pulse width extension
Data Source
AI summary
A semiconductor memory device includes: a high frequency signal control unit for receiving an external command address signal, removing noise and glitch from the external command address signal and outputting a first command address signal; a pulse width control unit for controlling a pulse width of the first command address signal or maintaining the pulse width of the first command address signal and outputting a second command address signal with a predetermined pulse width; a refresh operation control unit for generating a row address for a refresh operation in response to the second command address signal; and a memory cell array for performing the a refresh operation in response to the row address.