Dual-Output Sense Amplifier Latch for Faster Memory Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional sense amplifier and latching schemes in memory systems suffer from slow memory access times due to underutilization of both outputs of the sense amplifier, leading to complex stacked gates and inefficient latch driving.
Innovation Solution
The proposed solution involves a sense amplifier circuit that actively drives both outputs to a latching circuit, utilizing a primary driver and a secondary driver with PMOS and NMOS pull-up and pull-down devices, respectively, to improve latch performance and reduce circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If only one output of the sense amplifier is used to actively drive the latch, then the circuit complexity is reduced, but the memory access time increases
Solution Approach 1:
The patent combines both outputs of the sense amplifier (first output data line true signal and second output data line complement signal) to actively drive the latch circuit through primary and secondary drivers. This merging of both outputs resolves the contradiction by utilizing both signals simultaneously to drive the latch, reducing access time while maintaining manageable circuit complexity through systematic organization of the driving circuitry.
Solution Approach 2:
The sense amplifier precharges both output lines before the read operation, and the latch circuit is designed with both primary and secondary drivers ready to activate. This preliminary preparation of both output paths enables faster response when the read operation occurs, addressing the time penalty issue while keeping the circuit structure organized.
2Device complexity
If a stacked inverter latch is used instead of a SR NOR latch, then the number of complex stacked gates is reduced, but the memory access time still increases due to underutilization of sense amplifier outputs
Solution Approach 1:
The patent merges both sense amplifier outputs to drive the latch circuit, with the first output driving the primary driver and the second output driving the secondary driver. This approach maintains the simplified latch structure while fully utilizing both sense amplifier outputs, thereby reducing access time without increasing gate complexity.
Solution Approach 2:
The latch circuit is designed to accept and utilize both the true signal and complement signal from the sense amplifier through separate driving paths. This multi-functional approach allows both outputs to contribute to the latching operation, improving speed while maintaining circuit simplicity.
3Speed
If both outputs of the sense amplifier are actively driven to the latching circuit, then the latching speed increases, but the circuit complexity increases
Solution Approach 1:
The patent segments the latch driving function into two independent paths: a primary driver driven by the first output data line true signal and a secondary driver driven by the second output data line complement signal. This segmentation allows both outputs to actively drive the latch simultaneously, increasing latching speed while keeping each driver path relatively simple and manageable.
Solution Approach 2:
The circuit dynamically activates both driving paths based on the sense amplifier outputs. The primary and secondary drivers are enabled by a sense amplifier enable signal, allowing the circuit to adaptively utilize both outputs when needed, improving speed while maintaining flexibility in circuit operation.
Data Source
AI summary
Approaches for a circuit are provided. The circuit includes a sense amplifier circuit which includes a plurality of transistors enabled by a sense amplifier enable signal to output a first output data line true signal and a second output data line complement signal to a latching circuit, and the latching circuit which includes a primary driver actively driven by the first output data line true signal and a secondary driver actively driven by the second output data line complement signal such that the latching circuit outputs a read global data line.