Trimming Reference Bias Level in Nonvolatile Memory Testing
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Solution Overview
Problem
Nonvolatile memory devices using variable resistance materials face challenges in accurately determining the reference bias level, leading to inconsistencies in data storage and retrieval due to variations in resistance dispersions, resulting in fail bits during testing.
Innovation Solution
A method is introduced to monitor resistance dispersions and determine candidate reference bias levels, upper, and lower test bias levels, calculating the number of fail bits to trim the reference bias level, minimizing the sum of fail bits through a trimming circuit that adjusts the read circuit's bias to optimize data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a fixed reference bias level is used in nonvolatile memory devices, then the device structure remains simple, but the accuracy of data storage and retrieval deteriorates due to resistance dispersion variations
Solution Approach 1:
The patent implements dynamic reference bias level adjustment by introducing a trimming circuit that can modify the reference bias level based on measured resistance dispersions. The trimming circuit includes adjustable elements (such as switches connecting to different reference voltage sources or current sources) that allow the reference bias level to be dynamically optimized for each memory device or batch, thereby improving data storage and retrieval accuracy without requiring complete redesign of the memory cell structure
Solution Approach 2:
The patent changes the parameter of reference bias level from a fixed value to an adjustable parameter. By measuring resistance dispersions and using this information to determine optimal reference bias levels (through algorithms that analyze fail bit patterns at different bias levels), the system optimizes the reference bias level parameter for each specific memory device, transforming a static parameter into a dynamic one that adapts to manufacturing variations
2Reliability
If resistance dispersion variations are not accounted for, then the testing process remains simple, but the number of fail bits increases due to inaccurate reference bias level determination
Solution Approach 1:
The patent implements a feedback mechanism where resistance dispersion measurements are used to adjust the reference bias level. The testing process measures resistance dispersions at multiple candidate reference bias levels, determines which level minimizes fail bits, and uses this information to set the optimal reference bias level for subsequent operations. This closed-loop feedback approach systematically reduces fail bits by continuously optimizing the reference bias level based on actual device performance
Solution Approach 2:
The patent performs preliminary testing and measurement of resistance dispersions before finalizing the reference bias level for data storage and retrieval operations. By conducting preliminary tests at multiple candidate bias levels and analyzing the resulting fail bit patterns, the system determines the optimal reference bias level in advance, allowing subsequent operations to proceed with optimized parameters and reduced error rates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes the number of fail bits by adjusting the reference bias level, enhancing the accuracy and reliability of data storage and retrieval in nonvolatile memory devices.
Implementation Method 1
A state of a phase change material is changed to a crystal state or an amorphous state while the phase change material is cooled after being heated. The phase change material in a crystal state has relatively low resistance, and the phase change material in an amorphous state has a relatively high resistance.
Data Source
AI summary
A method for testing a nonvolatile memory device includes: monitoring a first resistance dispersion and a second resistance dispersion of a nonvolatile memory device, determining a lower test bias level and an upper test bias level that are disposed on opposite sides of a reference bias level, calculating the number of first fail bits generated in the first resistance dispersion based on the lower test bias level and the number of second fail bits generated in the second resistance dispersion based on the upper test bias level, determining a selected reference bias level using the number of the first fail bits and the number of the second fail bits, and trimming the reference bias level to the selected bias level.