Cycle-Switched Logic Interconnect for Reconfigurable Data Processing
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Solution Overview
Problem
Existing data processing devices require extensive wiring resources to dynamically reconfigure circuits, leading to inefficient utilization of hardware resources and increased complexity in implementing algorithms.
Innovation Solution
A data processing unit with logic elements, acquisition units, and post units that switch connections on a cycle-by-cycle basis, allowing for dynamic reconfiguration of circuits without forming permanent paths, thereby optimizing hardware utilization and reducing wiring needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If circuits are dynamically reconfigured on a cycle-by-cycle basis, then hardware utilization efficiency and processing speed are improved, but wiring resources are excessively consumed
Solution Approach 1:
The patent implements dynamic circuit reconfiguration by enabling logic elements to change their connection states on a cycle-by-cycle basis. The acquisition unit and post unit dynamically switch connections between logic element inputs/outputs and channels, allowing the same physical wiring to serve multiple logical configurations over time, thereby reducing the total wiring resources needed while maintaining high processing speed.
Solution Approach 2:
The system employs periodic switching of acquisition and post units in synchronized cycles. By alternating the activation of acquisition units and post units in a periodic manner, the patent enables time-division multiplexing of wiring resources, where channels are shared across different logic elements at different time cycles, reducing overall wiring requirements while maintaining continuous high-speed processing capability.
2Adaptability or versatility
If wiring resources are increased to support dynamic reconfiguration, then more algorithms can be implemented, but hardware resource occupation increases
Solution Approach 1:
The patent makes wiring resources universal by designing channels that can be dynamically connected to different logic elements based on the current operational cycle. The same physical channel can serve multiple different algorithmic functions at different times, allowing a limited set of wiring resources to support a wide variety of algorithms through time-division multiplexing and dynamic reconfiguration.
Solution Approach 2:
The system dynamically reconfigures the mapping between logic elements and channels on a cycle-by-cycle basis. By changing which logic elements are connected to which channels at different times, the patent enables a small number of physical wiring resources to support many different algorithmic implementations, achieving high adaptability without proportionally increasing hardware resource occupation.
3Ease of operation
If connections are permanently established between logic elements, then data transfer is simple, but reconfiguration capability is lost
Solution Approach 1:
The patent implements periodic switching between different connection configurations. During each cycle, acquisition units and post units are activated in a periodic pattern that establishes temporary connections between logic elements and channels. These connections remain stable during each cycle for simple data transfer, then switch to new configurations in the next cycle, providing both operational simplicity and reconfiguration capability through time-division multiplexing.
Solution Approach 2:
The system dynamically controls the connection state between logic elements and channels using acquisition units and post units that can switch connections on and off. This dynamic control allows connections to be established and maintained during each operational cycle for simple data transfer, then reconfigured in subsequent cycles to provide adaptability and reconfiguration capability without sacrificing either ease of operation or versatility.
Data Source
AI summary
A data processing device includes a data processing unit including a plurality of elements and wiring groups that connect the plurality of elements, wherein respective elements in the plurality of elements include: a logic element; an acquisition unit that switches on and off an input side of the logic element for any wire out of the wiring groups on a cycle-by-cycle basis to latch input data; and a post unit that switches on and off an output side of the logic element for any wire out of the wiring groups on a cycle-by-cycle basis, and the data processing unit also includes a timing control unit that controls logic executed by the logic element and functions of the acquisition unit and the post unit on a cycle-by-cycle basis.