Pipelined Embedded Memory Coherency Using Address Match Selection

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Solution Overview

Problem

Existing embedded memory blocks in programmable logic devices face challenges in maintaining data coherency between concurrent memory reads and writes, especially with increased pipelining, which can result in non-current data being read due to early presentation of read addresses, leading to unpredictable outputs.

Innovation Solution

The implementation of a memory circuit with registers, comparator circuitry, and selection circuitry that stores read and write addresses and data across multiple clock cycles, determines address matches, and outputs appropriate data based on these comparisons to ensure coherency, regardless of pipelining levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If read address is presented to memory early to enable pipelining, then read data availability is improved, but data coherency deteriorates causing non-current data to be read

Engineering Contradiction:

Improveread data availabilityVSAvoiddata coherency

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent stores the read address in a register during the first clock cycle before the actual memory read occurs. This preliminary storage allows the system to capture the intended read address and use it for comparison with write addresses in subsequent cycles, ensuring that the correct data is selected even when reads are pipelined ahead of writes

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements comparator circuitry that continuously compares the stored read address with incoming write addresses. This feedback mechanism detects address matches and generates control signals that redirect data flow to ensure current write data is returned when addresses match, thereby maintaining data coherency despite pipelining

Inventive Principle:

Principle #23Feedback

2Productivity

If pipelining is increased to improve throughput, then memory access speed is improved, but data coherency maintenance becomes more difficult

Engineering Contradiction:

Improvememory access speedVSAvoidcoherency maintenance complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary data path that includes multiplexers controlled by comparator outputs. These multiplexers act as mediators between the memory output and the read data output, selectively routing either the memory read data or the current write data based on address match detection, thereby simplifying coherency maintenance despite increased pipelining

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9558796B2Systems and methods for maintaining memory access coherency in embedded memory blocks

Publication Date: 2017.01.31 ALTERA CORP

AI summary

Enhanced memory circuits are described that maintain coherency between concurrent memory reads and writes in a pipelined memory architecture. The described memory circuits can maintain data coherency regardless of the amount of pipelining applied to the memory inputs and/or outputs. Moreover, these memory circuits may be implemented as dedicated hard circuits in a field programmable gate array (FPGA) or other programmable logic device (PLD), and can be supplemented with user-configurable logic to achieve coherency in a variety of applications.