Tri-State Driver Circuit With Automatic High-Impedance Timing
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Solution Overview
Problem
Conventional tri-state driver circuits in high-speed integrated circuits require additional circuitry and power for correctly timing a separate enable signal, leading to increased substrate area consumption and power usage.
Innovation Solution
A signal driver circuit that provides automatic tri-state control using a true input signal and its complement, eliminating the need for a separate enable signal by utilizing a delay line, boost circuit, and enable circuit to manage logic levels and impedance states without additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate enable signal is used to control the high-impedance state of the driver circuit, then the driver circuit can be tri-stated, but additional circuitry is required that consumes substrate area and electrical power
Solution Approach 1:
The patent combines the enable signal generation function with the existing input signal processing circuitry. The delay line and logic circuitry that already process the input signal IN are used to generate the enable signal, merging multiple functions into existing components and eliminating the need for separate enable signal circuitry.
Solution Approach 2:
The input signal processing circuitry is designed to serve multiple functions: it processes the input signal IN for the driver output and simultaneously generates the enable signal for tri-state control. This multi-functionality eliminates dedicated enable signal circuitry while maintaining tri-state capability.
2Adaptability or versatility
If a separate enable signal is used to control the high-impedance state, then the driver circuit can be tri-stated, but electrical power is consumed by the additional circuitry
Solution Approach 1:
The enable signal generation is merged with the input signal processing function, so that the same circuitry that must operate to process the input signal is used to generate the enable signal. This eliminates additional power-consuming enable signal circuitry while maintaining tri-state functionality.
Solution Approach 2:
The driver circuit generates its own enable signal using its existing input signal processing circuitry, eliminating the need for external enable signal sources and their associated power consumption. The circuit serves itself by producing the control signal from its own operational signals.
3Reliability
If the timing of the enable signal is closely controlled, then the driver circuit enters and exits the tri-state condition without interfering with the output signal, but additional circuitry is required that consumes substrate area
Solution Approach 1:
The timing control function is merged with the input signal processing circuitry. The delay line that is already necessary for signal processing is used to provide the precise timing for the enable signal, eliminating the need for separate timing control circuitry and reducing substrate area.
Solution Approach 2:
The input signal processing circuitry performs multiple functions including signal processing and timing control for the enable signal. This multi-functionality achieves reliable timing control without requiring additional dedicated timing circuitry that would consume substrate area.
Data Source
AI summary
Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay relative to the input signal. The output stage receives the delayed input signal and further receives the complement of the input signal. The output stage couples an output node to a first voltage in response to a complement of the input signal having a first logic level and couples the output to a second voltage in response to the complement of the input signal having a second logic level. The output stage further decouples the output from the first or second voltage in response to receiving the delayed input signal to provide a high-impedance at the output node.