Non-Volatile Latch Switching for Power-Off Data Retention
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Solution Overview
Problem
Conventional latches are volatile, losing data when power is turned off, as they cannot store data persistently.
Innovation Solution
A non-volatile latch circuit design incorporating a latch circuit, switch circuits, and a non-volatile memory device, where the switch circuits control the coupling of the non-volatile memory device to programming and reference voltages based on latched data and state transformation conditions, allowing data to be stored and retained even after power is turned off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional latch is used, then the latch can operate with simple circuitry and fast access, but the data is lost when power is turned off
Solution Approach 1:
The patent merges a conventional latch circuit with a non-volatile memory device into a unified non-volatile latch structure. The latch circuit (comprising first and second cross-coupled inverters) is directly integrated with the non-volatile memory device, allowing the system to simultaneously achieve fast latch operation and persistent data storage. The memory device is coupled to the latch output through switch circuits, creating a combined structure that maintains both volatility and non-volatility characteristics.
Solution Approach 2:
The patent implements preliminary action by storing latch data into the non-volatile memory device before power is turned off. The control circuit monitors the power state and activates the memory storage function in advance, ensuring data is preserved in the non-volatile memory before the volatile latch loses its state. This preemptive data transfer prevents data loss without requiring complex redesign of the fundamental latch operation.
2Reliability
If power is continuously supplied to maintain data, then data retention is ensured, but power consumption increases
Solution Approach 1:
The patent employs periodic action through controlled power supply management. Instead of continuous power supply, the system uses periodic power cycles with controlled transitions between active and low-power states. The memory control circuit activates the non-volatile memory storage function during specific periods (when data needs to be preserved) while allowing the latch to enter low-power states otherwise. This periodic operation reduces average power consumption while maintaining data retention reliability.
Solution Approach 2:
The patent introduces switch circuits as intermediary elements between the latch circuit and the non-volatile memory device. These switches (first and second switch circuits) act as mediators that control the coupling between the volatile latch and the non-volatile memory. By using these intermediary switches, the system can selectively connect or disconnect power and data paths, enabling the latch to operate in low-power modes while still maintaining data integrity through the non-volatile memory when needed.
3Reliability
If a non-volatile memory device is integrated, then data persistence is achieved, but access speed may decrease
Solution Approach 1:
The patent segments the memory system into two distinct functional parts: a volatile latch circuit for fast data access and a non-volatile memory device for persistent storage. The latch circuit maintains actively used data for rapid read/write operations, while the non-volatile memory stores backup data for persistence. This segmentation allows the system to achieve both fast access (through the latch) and data persistence (through the non-volatile memory) without compromising either function. The switch circuits enable selective access to either component based on operational requirements.
Data Source
AI summary
Provided is a non-volatile latch, which includes a latch circuit, a first switch circuit, a non-volatile memory device, a second switch circuit and a third switch circuit. A first terminal of the first switch circuit is coupled to a first output terminal of the latch circuit. The first switch circuit is turned off in a normal operation period. A first terminal of the non-volatile memory device is coupled to a second terminal of the first switch circuit. A second terminal of the non-volatile memory device is coupled to a programming voltage via the second switch circuit. In a store period, according to latched data of the latch circuit and a state transformation condition of the non-volatile memory device, the third switch circuit can dynamically determine whether to couple the first terminal of the non-volatile memory device to a reference voltage.