FPGA Signal Access via Address-Unit Sorted Bit Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for accessing signals in programmable logic devices, such as FPGAs, are limited by slow access speeds and require modifications to the device, restricting the ability to efficiently read or write signal values without changing the configuration, which hampers simulation and control of dynamic systems.
Innovation Solution
A method and device that enable bitwise access to signal values by sorting access requests based on address units, allowing sequential access to bits within an address unit, independent of the signal, and using a buffer to store and manage read and write operations, thereby accelerating access without modifying the configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If access to signal values is performed through the configuration level of the FPGA, then signal values can be read during execution, but the access speed is limited due to the need to read all words from the start of the address unit to the requested bit
Solution Approach 1:
The patent applies preliminary action by pre-sorting access requests according to their address units and address offsets before execution. This sorting is performed in advance, allowing the system to process requests in an optimized sequence that minimizes redundant reads. By organizing requests beforehand based on their target address units and the position of bits within those units, the system可以避免重复读取相同的数据范围，从而加速访问过程
Solution Approach 2:
The patent changes the parameter of access request organization by sorting requests based on address unit and address offset parameters. Instead of processing requests in the order they are received or based on signal grouping, the system reorganizes them according to the physical memory structure (address units) and the position of bits within those units. This parameter-based reorganization enables more efficient sequential reading through the configuration level
2Speed
If modifications are made to the programmable logic device to improve access speed, then access performance increases, but the device complexity and manufacturing requirements increase
Solution Approach 1:
The patent introduces an intermediary component - the access request sorting mechanism - that sits between the user/requestor and the FPGA configuration level. This sorting mechanism acts as a mediator that translates arbitrary access requests into an optimized sequence of reads and writes to the configuration level. By inserting this intermediary layer, the system achieves faster access without modifying the fundamental structure of the FPGA device itself, thus avoiding increased device complexity and manufacturing requirements
3Ease of operation
If all words from the start of the address unit to the requested bit are read, then the requested bit can be accessed, but the number of reads increases and access time is extended
Solution Approach 1:
The patent applies segmentation by dividing access requests into groups based on their target address units. Instead of processing each request independently (which would cause redundant reads of the same address units), the system segments requests by their address unit destination and processes all requests targeting the same address unit together. This segmentation allows the system to read each address unit only once and serve multiple requests from that single read operation, thereby improving access efficiency while maintaining ease of operation
Data Source
AI summary
A method for accessing signals of a programmable logic device having a functional level and a configuration level at run time when the programmable logic device is executing a predefined configuration. An access to at least one signal value that has a number of bits is requested. The individual bits in the configuration are each located in an address unit with one address offset apiece such that one or more bits of a signal value are located in one address unit. A bitwise access to the requested signal values takes place, wherein the accesses to the individual bits are sorted as a function of the address unit containing the applicable bit in such a manner that the accesses to all bits located in an address unit take place in sequence as a function of the address offset, independently of the signal containing the applicable bit.