Quadra-Phase Clock Generator Without Frequency Division Delay
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Solution Overview
Problem
Conventional quadra-phase designs for generating clock signals require long initialization times and high power consumption, and often employ clock dividers that reduce the frequency and increase the period of multi-phase output signals.
Innovation Solution
A quadra-phase generator architecture that uses delay circuits to produce quadrature clock signals with minimal initialization time, achieving full input clock frequency over a wide operational bandwidth, by introducing a delay Δt that allows rising and falling edges of clock signals to align closely, thus enabling efficient generation of 0-degree, 90-degree, 180-degree, and 270-degree phase outputs within 1-2 clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional PLL with multiple adjustable delay lines or analog cells is used, then multi-phase output signals can be generated, but initialization time becomes long and power consumption increases
Solution Approach 1:
The patent divides the clock signal generation into separate path segments: a first path generating a first clock signal and a second path generating a second clock signal with complementary phases. This segmentation allows independent optimization of each path, achieving accurate quadrature phases without requiring long initialization periods associated with conventional PLL delay lines.
Solution Approach 2:
Instead of using a single clock signal and creating delays to generate multi-phase signals (the conventional approach), the patent inverts the approach by generating two clock signals with complementary phases and then combining them. This inversion eliminates the need for long delay lines and reduces initialization time while maintaining phase accuracy.
2Measurement precision
If conventional PLL with adjustable delay lines is used, then multi-phase output signals can be generated, but power consumption becomes high
Solution Approach 1:
The patent extracts and eliminates the power-consuming components from the conventional PLL architecture. Specifically, it removes the need for multiple adjustable delay lines and analog cells that consume significant power, replacing them with a simpler dual-path clock generation approach that achieves the same quadrature phase output with lower power consumption.
Solution Approach 2:
The patent employs simpler, less power-consuming clock generation components in place of complex PLL circuits. By using basic clock signal generation and combination logic rather than power-hungry adjustable delay lines and analog cells, the system achieves phase-accurate quadrature signals with significantly reduced power consumption.
3Measurement precision
If clock divider is used to generate multi-phase signals, then phase offset of 90 degrees can be achieved, but frequency is halved and period is doubled
Solution Approach 1:
Instead of dividing the clock frequency and using delay elements to create phase offsets (which halves the frequency), the patent inverts the approach by generating two full-frequency clock signals with complementary phases and combining them. This maintains the full input clock frequency in the output while achieving accurate 90-degree phase offsets.
Solution Approach 2:
The patent transitions from a single-dimension approach (frequency division followed by phase shifting) to a two-dimension approach: generating clock signals in the time domain with complementary phases and then combining them in the signal domain. This dimensional change allows maintaining full frequency while achieving precise phase offsets without the limitations of clock division.
Data Source
AI summary
Apparatuses are provided for a quadra-phase clock signal generator. An example apparatus includes a first delay circuit configured to receive a first input clock signal generating a first delayed clock signal. A first phase mixer is provided communicatively coupled to the first delay circuit and configured to receive the first delayed clock signal at a first input and a second input clock signal at a second input. The first phase mixer may then generate a first output clock signal at a first output node responsive, at least in part, to mixing of the first delayed clock signal and the second input clock signal.