Soft Error Sensitivity Mapping for Selective Logic Reconfiguration
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Solution Overview
Problem
Programmable integrated circuits face frequent disruptions due to soft errors caused by radiation, leading to unnecessary reconfigurations, as existing error detection techniques cannot differentiate between critical and non-critical bits, resulting in higher design effective failure rates.
Innovation Solution
An integrated circuit with error detection and sensitivity processing circuitry that uses a cyclic redundancy check (CRC) to detect soft errors and a sensitivity processor to determine the criticality of the errors by accessing a sensitivity map header (SMH) file, allowing for targeted corrective actions such as partial reconfiguration based on the sensitivity tags assigned to different logic regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection circuitry monitors the entire array of CRAM cells and triggers reconfiguration upon detecting any soft error, then system reliability is improved, but system disruptions increase due to unnecessary reconfigurations of non-critical bits
Solution Approach 1:
The patent segments the CRAM cell array into multiple logic regions and introduces sensitivity tags to classify bits as critical or non-critical. When a soft error is detected, the system only triggers reconfiguration for regions containing critical bits, rather than reconfiguring the entire array. This segmentation approach maintains system reliability by addressing critical errors while avoiding unnecessary disruptions from non-critical errors.
Solution Approach 2:
The patent applies local quality by differentiating between critical and non-critical bits within the CRAM cell array using sensitivity tags. Each bit is assigned a sensitivity tag indicating its importance to system functionality. This allows the error detection circuitry to apply different corrective actions locally: full reconfiguration for critical bits and no reconfiguration for non-critical bits, thereby reducing unnecessary system disruptions while maintaining reliability.
2Reliability
If the entire programmable device is reconfigured every time a soft error is detected, then system reliability is improved, but productivity decreases due to frequent reconfigurations
Solution Approach 1:
The patent segments the device into logic regions with different sensitivity tags. When a soft error occurs, the system identifies the sensitivity tag of the affected bit and only reconfigures the specific logic region if the bit is critical. This selective reconfiguration approach maintains system reliability for critical functions while preserving productivity by avoiding reconfigurations of non-critical regions, thereby increasing system uptime.
Solution Approach 2:
The patent implements partial action by performing reconfiguration only when necessary - specifically, only when a soft error affects a critical bit. For non-critical bits, no reconfiguration is performed. This partial reconfiguration strategy ensures reliability for critical operations while minimizing productivity loss by avoiding unnecessary reconfigurations, thus maintaining higher system uptime.
3Loss of time
If sensitivity processing circuitry is added to differentiate between critical and non-critical bits, then system disruptions are reduced, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing sensitivity tags for each CRAM cell during the design phase. These sensitivity tags indicate whether each bit is critical or non-critical to system functionality. During operation, the error detection circuitry simply reads the pre-stored sensitivity tag to determine the appropriate action, avoiding the need for complex real-time analysis and reducing both system disruptions and operational complexity.
Solution Approach 2:
The patent uses copying by creating a sensitivity map that replicates the criticality information of each CRAM cell in a readily accessible format. This sensitivity map is generated during design and stored in the device, allowing the error detection circuitry to quickly determine the criticality of any bit without complex real-time computation. This copying approach reduces device complexity while enabling differentiated error handling to minimize system disruptions.
Data Source
AI summary
Integrated circuits with single event upset (SEU) detection circuitry are provided. The SEU detection circuitry may include an error detection block for detecting soft errors and a sensitivity processor that determines whether or not to correct the detected soft errors. The sensitivity processor may be used to access a sensitivity map header (SMH) file that is stored on external memory. The sensitivity map header file contains information that can help identify which logic region on the integrated circuit the soft error affects and whether or not that soft error can critically cause functional failure for the integrated circuit. Depending on the criticality of the soft error, different corrective actions may be taken.