Multi-Channel Data Latch Timing to Prevent IC Cross-Talk

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Solution Overview

Problem

Integrated circuits face distortion and deformation of data waveforms due to reflection, inter-symbol interference, cross-talk, and skin effects, especially in multi-drop semiconductor systems, which complicates circuit design and increases manufacturing costs when using physical shielding or data encoding techniques.

Innovation Solution

The integrated circuit design includes a transmitter and receiver with multiple output and input circuits that select and synchronize latch clock signals to transmit data through different channels with distinct phases, preventing cross-talk distortion by aligning input and output data waveforms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If physical shielding technique or data encoding technique is applied to multi-drop semiconductor systems, then cross-talk phenomenon is removed, but circuit complexity increases and manufacturing costs increase

Engineering Contradiction:
Improvecross-talk phenomenonVSAvoidcircuit complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by modifying the timing parameters of data transmission. Specifically, it transmits data on alternating clock cycles (even cycles for first channel, odd cycles for second channel) rather than using complex shielding or encoding techniques. This temporal parameter change effectively eliminates cross-talk between adjacent channels while maintaining simple circuit design and low manufacturing costs.

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If termination technique is used, then reflection phenomenon is removed, but manufacturing costs increase

Engineering Contradiction:
Improvereflection phenomenonVSAvoidmanufacturing costs
Core Design Contradiction:
Object-affected harmful factorsVSEase of manufacture

Solution Approach 1:

The patent uses parameter changes in the timing domain to address signal integrity issues. By staggering the data transmission timing between adjacent channels (even vs. odd clock cycles), the patent eliminates the need for termination techniques and associated increased manufacturing costs, while still removing reflection phenomena through proper timing alignment.

Inventive Principle:
Principle #35Parameter changes

3Object-affected harmful factors

If equalization technique is used, then inter-symbol interference phenomenon is removed, but circuit complexity increases

Engineering Contradiction:
Improveinter-symbol interference phenomenonVSAvoidcircuit complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies equalization effects through parameter changes in the timing domain rather than using complex equalization circuits. By carefully controlling the phase and timing of data transmission on different channels, the patent eliminates inter-symbol interference while keeping the circuit design simple and avoiding the complexity of traditional equalization techniques.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9843316B2Integrated circuits relating to transmission data and latch clock signals
Publication Date: 2017.12.12 SK HYNIX INC
  • US9843316B2 patent drawing
  • US9843316B2 patent drawing
  • US9843316B2 patent drawing

AI summary

An integrated circuit may be provided. The integrated circuit may include a transmitter and a receiver. The transmitter outputs first transmission data to a first channel and outputs second transmission data to a second channel. The phase of the first transmission data transmitted through the first channel is different from a phase of the second transmission data transmitted through the second channel.