Configuration Memory Circuit Layout for Lower Data Line Leakage
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Solution Overview
Problem
In programmable integrated circuits, the voltage swing required for address signals to memory cells exceeds the maximum tolerable voltage swing of thin-gate devices, leading to reliability issues and defects due to data line leakage, necessitating the use of large level shifters or thick-gate devices that increase cost and power consumption.
Innovation Solution
The implementation of dual mode memory cells that can operate in either lookup-table mode or memory mode, coupled in a hierarchical data line routing arrangement, allowing address signals to be driven to ground voltage instead of negative voltage, reducing data line leakage and eliminating the need for large level shifters and thick-gate devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address signals are driven from overdrive voltage (1.1 V) to negative voltage (−0.1 V) to reduce leakage and improve read/write margin, then leakage current is reduced and read/write margin is improved, but the voltage swing (1.2 V) exceeds the maximum tolerable voltage swing of thin-gate devices (1.13 V), causing reliability issues and device breakdown
Solution Approach 1:
The patent segments the data line into multiple hierarchical levels (local data lines at the memory cell level, column data lines at the column level, and global data lines at the array level). This segmentation allows address signals to be driven only to ground voltage (0 V) rather than negative voltage, reducing the voltage swing to within the tolerable range for thin-gate devices while maintaining low leakage current through the hierarchical structure.
Solution Approach 2:
The patent introduces pass gate transistors as intermediary elements between memory cells and data lines. These pass gates act as mediators that control the coupling between local data lines and column/global data lines, enabling the address signals to operate within safe voltage ranges while still achieving the desired leakage reduction through selective coupling.
2Reliability
If large level shifters and thick-gate devices are used to handle the voltage swing requirement, then the voltage swing issue is resolved, but power consumption and device cost increase
Solution Approach 1:
By segmenting the data line hierarchy and limiting address signal voltage swing to ground level (0 V) rather than requiring negative voltage, the patent eliminates the need for power-hungry level shifters and thick-gate devices. The segmentation allows thin-gate devices to operate within their safe voltage range while achieving the same leakage reduction effect.
Solution Approach 2:
The patent replaces expensive and power-consuming thick-gate devices and large level shifters with simpler, cheaper thin-gate devices that operate within safe voltage ranges. The hierarchical data line structure with pass gates provides an economical solution that achieves the same functional outcome without the high power consumption and cost of the alternative approach.
3Loss of energy
If hierarchical data line routing arrangement is implemented, then data line leakage is reduced and address signals can be driven to ground voltage, but the data line routing complexity increases
Solution Approach 1:
The patent divides the data line into a hierarchical structure with local data lines connected to individual memory cells, column data lines serving groups of cells, and global data lines serving the entire array. This segmentation reduces data line leakage by limiting the capacitance that address signals must charge/discharge, while the systematic hierarchical organization manages the routing complexity in a structured manner.
Solution Approach 2:
The patent introduces a hierarchical dimension to the data line routing, organizing memory cells into groups and columns with corresponding hierarchical data line levels. This dimensional organization reduces leakage by creating multiple levels of signal distribution, where each level serves a specific scope, thereby managing complexity through structured layering rather than flat routing.
Data Source
AI summary
Integrated circuits may include dual mode memory cells. Dual mode memory cells may be operated in a lookup-table mode or a memory mode. A dual mode memory cell may have configuration ports for supporting a configuration operation and user ports for supporting a user mode operation. When performing configuration operations in the memory mode, the configuration ports may be gated off to prevent existing user data from being accessed. Each column of memory cells may be arranged into groups. Each group of memory cells in a column may be connected to a respective local data line, which is connected to a global data line via a switch. The switch may be selectively activated to short the local data line to the global data line. Configured in this hierarchical data line architecture, leakage at the global data line can dramatically be reduced, and the memory cell read margin is improved.