Built-In Level-Shifter Latch for Low-Leakage Dual-Rail SRAM

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Dual-rail SRAM devices face issues with increased leakage and area occupancy due to separate latches and level shifters, which result in gate delay latency and leakage penalties.

Innovation Solution

A combined latch/level shifter switching circuit that operates in two modes: a transparent phase for level shifting and a latch phase for data storage, reducing leakage current and latency by integrating both functions into a single circuit with reduced transistor count.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate level shifters and latches are used in dual-rail SRAM devices, then voltage level shifting and data latching functions are achieved, but area occupancy and device complexity increase

Engineering Contradiction:

Improvevoltage level shifting and data latching functionalityVSAvoidarea occupancy

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines the level shifter and latch into a single integrated circuit block that performs both voltage level shifting and data latching functions simultaneously. This merging eliminates the need for separate level shifter and latch circuits, thereby reducing area occupancy while maintaining both required functionalities.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The integrated circuit is designed to perform multiple functions: it acts as a level shifter for voltage domain crossing and as a latch for data storage. This multi-functional design allows a single circuit to replace what would traditionally require separate dedicated circuits for each function.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If separate level shifters and latches are used in dual-rail SRAM devices, then voltage level shifting and data latching functions are achieved, but gate delay latency increases

Engineering Contradiction:

Improvevoltage level shifting and data latching functionalityVSAvoidgate delay latency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

By merging the level shifter and latch into a single circuit, the patent eliminates the sequential operation required when using separate circuits. The integrated design allows simultaneous execution of level shifting and latching operations, thereby reducing the total gate delay latency.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If separate level shifters and latches are used in dual-rail SRAM devices, then voltage level shifting and data latching functions are achieved, but leakage current increases

Engineering Contradiction:

Improvevoltage level shifting and data latching functionalityVSAvoidleakage current

Core Design Contradiction:

Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The integrated circuit shares common transistors and circuit paths between the level shifter and latch functions. This sharing reduces the total number of transistors compared to separate implementations, thereby reducing overall leakage current while maintaining both functionalities.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9934845B2Latch with built-in level shifter

Publication Date: 2018.04.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device comprising a first supply voltage, a second supply voltage, different from the first supply voltage; and a switching circuit. The switching circuit comprises an input configured to receive an input signal corresponding to the first supply voltage and an output configured to output an output signal corresponding to the second supply voltage. The switching circuit is a combined latch with a built-in level shifter that provides latching functionality and level shifting functionality and a leakage path is cut-off when the switching circuit is providing latching functionality.