Push-Pull Buffer Phase Interpolators With Linear Clock Slopes
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Solution Overview
Problem
Current phase interpolators suffer from non-linear behavior due to the RC effect caused by load resistors in current mode logic buffers, leading to undesirable variations in the slope of output clock signals, which affects the linearity of phase control.
Innovation Solution
The use of push-pull buffers, which employ pairs of n-FET and p-FET transistors, generates output clock signals with a more linear slope, improving the linearity of phase interpolators by eliminating the need for loading capacitors and reducing semiconductor chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current mode logic buffers with load resistors are used, then the phase interpolator can operate, but the RC effect causes non-linear behavior and slope variations in output clock signals
Solution Approach 1:
The patent removes the load resistors that cause the RC effect from the buffer circuit. By extracting this harmful component, the non-linear behavior and slope variations are eliminated, improving phase control linearity without compromising buffer functionality
Solution Approach 2:
The patent changes the buffer output configuration from resistive loading to direct transistor output. This parameter change in the circuit topology eliminates the RC time constant that causes non-linearity, allowing the buffer to drive the phase interpolator inputs directly with linear waveforms
2Reliability
If loading capacitors are added to compensate for RC effects, then linearity may improve, but semiconductor chip area and power consumption increase
Solution Approach 1:
The patent eliminates the need for loading capacitors by removing the source of non-linearity (load resistors) in the first place. This preventive approach avoids the need for compensating components, saving chip area while maintaining output signal linearity
Solution Approach 2:
The patent converts the potentially harmful RC effect into a benefit by redesigning the buffer to inherently produce linear waveforms. The buffer's direct transistor output becomes advantageous, providing clean square waves without requiring additional capacitive loading for linearity compensation
3Reliability
If loading capacitors are added to compensate for RC effects, then linearity may improve, but power consumption increases
Solution Approach 1:
The patent removes load resistors that would require power to drive RC time constants, eliminating the source of non-linearity. This extraction approach improves linearity without the power penalty of driving capacitive loads through resistive elements
Solution Approach 2:
The buffer circuit serves itself by directly driving the phase interpolator inputs with clean waveforms. The transistor outputs inherently provide the needed signal integrity without requiring external capacitors, reducing overall power consumption while maintaining linearity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The push-pull buffers provide improved linearity and reduced variation across different process corners, enhancing the performance of phase interpolators by maintaining consistent drive strength and eliminating the need for capacitors that introduce non-linearities.
Implementation Method 1
The use of push-pull buffers, which employ pairs of n-FET and p-FET transistors, generates output clock signals with a more linear slope
Data Source
AI summary
Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers.