Bi-Directional SCR ESD Protection Device With Layered Substrate
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Solution Overview
Problem
Bi-directional silicon-controlled rectifier (SCR) devices for electrostatic discharge (ESD) protection often exhibit deep snapback behavior, leading to low holding voltage and high on-resistance, which increases the likelihood of latch-up and degrades failure current, and increasing the N-well length to address this issue results in larger device size and higher on-resistance.
Innovation Solution
The ESD protection device is designed with a substrate structure featuring multiple layers with specific conductivity types and bridged regions, where the middle region of the second substrate layer is narrower than the first, and border regions are partially arranged over the middle and border regions of the first layer, allowing for a more efficient current path and reduced on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the N-well length is increased to increase the holding voltage of the SCR device, then the holding voltage is improved, but the device size increases and the on-resistance largely increases
Solution Approach 1:
The patent introduces a multi-layer substrate structure (first substrate layer, second substrate layer, third substrate layer) with vertical stacking, transforming the traditional planar SCR structure into a three-dimensional configuration. This dimensional change allows the holding voltage to be improved through the layered architecture without proportionally increasing the lateral device size.
Solution Approach 2:
The patent embeds multiple substrate layers within each other, where the second substrate layer is positioned over the first substrate layer, and the third substrate layer is positioned over the second substrate layer. This nested configuration allows compact integration while maintaining the necessary N-well length for adequate holding voltage.
2Reliability
If the N-well length is increased to increase the holding voltage of the SCR device, then the holding voltage is improved, but the on-resistance largely increases
Solution Approach 1:
The patent applies different conductivity types to different regions: the first substrate layer has first conductivity type, the second substrate layer has second conductivity type, and the third substrate layer has first conductivity type. This local differentiation of electrical properties optimizes the current conduction path, reducing on-resistance while maintaining adequate holding voltage through the layered structure.
Solution Approach 2:
The patent creates a composite semiconductor structure by combining multiple substrate layers with alternating conductivity types, forming a complex P-N-P-N structure. This composite configuration allows simultaneous optimization of holding voltage (through adequate N-well length in the second layer) and on-resistance (through the alternating conductivity types providing efficient current paths).
3Length of stationary object
If the middle region of the second substrate layer is made narrower to reduce device size, then the device size is reduced, but the current conduction capability may be affected
Solution Approach 1:
The patent compensates for the narrower middle region in the second substrate layer by providing additional current conduction paths through the first and third substrate layers. The multi-layer vertical structure distributes the current flow across multiple layers, maintaining adequate current conduction capability despite the reduced lateral width in the second layer.
Solution Approach 2:
The patent combines the current conduction functionality across multiple substrate layers, where the first, second, and third substrate layers collectively provide the current path. This merging of conduction paths across layers compensates for the narrower middle region while maintaining overall current conduction capability.
Data Source
AI summary
An ESD protection device may include a substrate having first and second substrate layers, and first and second bridged regions. Each substrate layer may include first and second border regions and a middle region laterally therebetween. Each bridged region may be arranged within the middle region and a respective border region of the second substrate layer. The middle region of the second substrate layer may be laterally narrower than the middle region of the first substrate layer. Each border region of the second substrate layer may be partially arranged over the middle region of the first substrate layer and partially arranged over a respective border region of the first substrate layer. The border regions of the substrate layers, and the bridged regions may have a first conductivity type, and the middle regions of the substrate layers may have a second conductivity type different from the first conductivity type.