Bi-Directional Split Gate NAND Flash Memory Structure
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Solution Overview
Problem
Prior art NAND flash memory structures require two row lines for each cell, leading to excessive high voltage control lines and are uni-directional in operation, which limits memory device pitch and efficiency.
Innovation Solution
A bi-directional NAND flash memory structure with a semiconductor substrate featuring a source and drain at the ends, utilizing a plurality of floating gates, control gates capacitively coupled to floating gates, and select gates positioned between floating gates, reducing the number of control lines needed and enabling bi-directional operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If two row lines are used for each cell (select gate and control gate), then cell operation is enabled, but the number of high voltage control lines increases excessively
Solution Approach 1:
The patent combines the select gate and control gate functions into a single shared row line structure. The control gate is positioned between floating gates and capacitively coupled to them, while the select gate is also positioned between floating gates, allowing both gates to share the same physical line infrastructure. This merging reduces the number of separate high voltage control lines required while maintaining full cell operation capability.
2Ease of manufacture
If traditional uni-directional NAND structure is used, then manufacturing is simplified, but memory device pitch is limited
Solution Approach 1:
The patent implements a bi-directional NAND structure where the select gate can select memory cells from either direction (left-to-right or right-to-left) along the string. This dynamic capability allows the memory array to be accessed from multiple directions, effectively doubling the usable pitch compared to traditional uni-directional structures, while maintaining compatibility with standard manufacturing processes.
3Quantity of substance
If control gates are positioned between floating gates with capacitive coupling, then line count per cell is reduced, but gate structure complexity increases
Solution Approach 1:
The control gate structure serves multiple functions simultaneously: it acts as a control electrode for the memory cell, provides capacitive coupling to the floating gate for charge storage, and functions as part of the shared row line infrastructure. This multi-functionality reduces the overall number of control lines needed while the gate structure itself, though more complex, integrates these functions in a manufacturable way using standard semiconductor processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the number of control lines required per cell, improving memory device pitch and enabling bi-directional operation, thus enhancing the efficiency and density of non-volatile memory arrays.
Implementation Method 1
Each control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates
Data Source
AI summary
A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.