Bifurcated Memory Management for Low Latency Access

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Solution Overview

Problem

Mobile computing devices face challenges in providing low latency access to software components like modem subsystem (MSS) code due to the high cost of direct random access memory (DRAM) and excessive latency in NAND storage elements, making it difficult to implement cost-effective and efficient memory management for wireless communications.

Innovation Solution

The implementation of bifurcated memory management, where a self-managed portion and a remotely managed portion of the memory element allow for low latency access to sensitive software elements while using a relatively inexpensive memory solution, with the host managing the unmanaged portion and the memory element managing its own portion, utilizing a communication bus for instruction transmission and address translation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If DRAM is used to store MSS code for low latency access, then access speed is improved, but cost increases

Engineering Contradiction:
Improveaccess speedVSAvoidcost
Core Design Contradiction:
SpeedVSEase of manufacture

Solution Approach 1:

The memory system is segmented into two distinct portions: a first portion (e.g., DRAM) optimized for low-latency access to critical MSS code, and a second portion (e.g., NAND flash) optimized for cost-effective storage of less time-sensitive data. This segmentation allows the system to achieve low latency for critical operations without incurring the high cost of using DRAM for entire memory storage.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If NAND storage is used to store MSS code to reduce cost, then cost is reduced, but access latency increases

Engineering Contradiction:
ImprovecostVSAvoidaccess latency
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

Different quality levels of memory are assigned to different data types based on their access requirements. The first portion of memory provides high-speed access characteristics for MSS code that requires low latency, while the second portion provides cost-effective storage for other data. This local quality differentiation ensures that each portion of memory operates at its optimal performance point.

Inventive Principle:
Principle #3Local quality

3Ease of operation

If the host manages the entire memory element, then control is centralized, but bus logic complexity increases

Engineering Contradiction:
ImprovecontrolVSAvoidbus logic
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The memory management system dynamically adapts its operation mode based on the type of data being accessed. For MSS code access, the system operates in a mode that leverages the first portion's low-latency characteristics with simplified bus logic. For other data operations, the system utilizes the second portion with appropriate management protocols. This dynamic adaptation optimizes both control efficiency and bus logic complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9880748B2Bifurcated memory management for memory elements
Publication Date: 2018.01.30 QUALCOMM INC
  • US9880748B2 patent drawing
  • US9880748B2 patent drawing
  • US9880748B2 patent drawing

AI summary

Bifurcated memory management for memory elements techniques are disclosed. In one aspect, a memory element includes a self-managed portion and a portion that is managed by a remote host. Software that needs low latency access may be stored in the portion of the memory element that is managed by the remote host and other software may be stored in the portion of the memory element that is managed by the memory element. By providing such bifurcated memory management of the memory element, a relatively inexpensive memory element may be used to store software while at the same time allowing low latency (albeit at low throughputs) access to sensitive software elements with minimal bus logic.