Memory Architecture Accessing/Allocation TRIZ Cases
- Virtual Trusted Computing Base for Secure Firmware Verification
A security memory loader verifies decryption keys and firmware integrity using a virtual trusted computing base.
- Nonvolatile Memory Data Security via Randomized Address Decoding
Bank decoder exchangers swap address subsignals with inverted signals on each power cycle, blocking unauthorized plaintext access without decryption overhead.
- Flash Memory Controller Background Garbage Collection Lifespan Index
A flash memory controller manages background garbage collection using a dynamic lifespan index to optimize system performance.
- Graph Memory Layout Optimization for Iterative Algorithm Speed
Reorders graph nodes in memory to improve cache locality, reducing TLB misses and accelerating iterative algorithms.
- TEE Shared Memory Data Transmission with Atomic Offset Management
Atomic offset variables eliminate locking overheads during asynchronous data transmission between trusted and non-trusted execution environments.
- Dynamic Cache Packing with Variable Bitmap Blocks
A dynamic cache packing method segments memory into variable-sized bitmap blocks to optimize storage density for data objects of varying sizes.
- Hybrid Storage Aggregate SSD HDD Tiering
A hybrid storage aggregate segments data across lower-latency solid state drives and higher-latency hard disk drives.
- Counters for Asynchronous Storage Busy Time Tracking
Asynchronous counters track memory sub-system busy time, avoiding performance penalties from timer management.
- Bifurcated Memory Management for Low Latency Access
Segmenting memory into self-managed and host-managed portions reduces bus logic complexity while maintaining low latency access for critical software.
- Power Gating Configuration Retention via Interrupt-Driven Memory
Interrupt-driven memory storage retains configuration data across power gating cycles, eliminating retention flip-flop area overhead.
- Hybrid Hardware-Software Cache Coherency for NUMA Systems
Segmented coherence management reduces memory bandwidth consumption while enabling independent scaling of processor and memory resources.
- Descriptor Cache for Flash Memory Address Mapping
Continuous meta data storage eliminates empty spaces between entries, improving address mapping speed and storage efficiency.
- GPU Parallel Garbage Collection Card Root Address Computation
A GPU computes card root addresses in parallel, reducing garbage collection pause times.
- Memory Card Formatting Device Directory Allocation
A formatting device allocates recording areas to directories based on a held ratio.
- NAND Memory Block Sub-Segmentation for Over-Provisioning Cost Reduction
Segmenting NAND blocks into sub-blocks maps special functions to specific portions while using remaining areas for host data, reducing over-provisioning costs.
- Flash Memory Controller Sequencer Reduces CPU Occupancy
A controller uses a sequencer to decode instruction codes for direct flash memory access.
- Tag Directory Aggregation for Cache Coherence
A tag directory aggregates individual acknowledgment messages from processor cores into a single consolidated message.
- DRAM Scrambling Circuitry for Data Security Without Speed Penalty
Memory controller scrambles DRAM bank select and data bits using volatile registers to maintain subsystem confidentiality.
- Storage Controller Zone Reallocation for NVMe Thermal Management
A storage controller reallocates memory blocks between zones based on temperature and hit ratio data.
- Set Associative Shadow Cache Way Prediction for Processor Stalling
Predicting shadow cache ways forwards parallel cache lines to eliminate processor stalling from conditional branch resolution.
- Selective Save Registers for Persistent Memory Data Persistence
Targeted save registers selectively persist critical volatile data to non-volatile memory, reducing unnecessary write operations and extending battery life.
- Session-Based Secure Access Control for Data Storage Systems
A data storage system manages write sessions by selectively assigning physical subareas and applying individual access protection to stored data.
- Hash Table Mask Length Computation for Longest Prefix Match Caching
A hash table uses dynamic mask lengths to access cache entries for destination addresses, enabling fast routing lookups via bit comparison.
- Pooled Memory Network Communication in Rack-Scale Architecture
Rack-scale architecture segments compute nodes from shared memory resources, reducing network traffic and improving thermal management through resource pooling.
- Flash Memory Page Identity Code for Power Loss Recovery
Flash memory pages store identity codes to identify the last written data segment, resolving incomplete write errors from sudden power loss.
- Cache Dirty Line Management for Power Failure Data Loss
A cache controller manages dirty lines using a segmented list to maintain data consistency during power interruptions.
- Storage Controller Linked List Protocol for Metadata Streaming
A storage controller generates a linked list interleaving user data and metadata entries to enable continuous data streaming without interruption.
- Memory Controller Resume Management via Retention Region ISP Loader
Storing a resume ISP loader in RAM retention region reduces wake-up time by avoiding complex code reloading during power saving mode transitions.
- Headless VM TLB Shootdown via Register Mediation
A headless virtual machine manager loads a VMID into an application processor register to issue a global TLB invalidate command.
- Multi-Level NVM Read Time Consistency via Voltage Level Comparison
Dynamic voltage comparison balancing eliminates read time variability in multi-level NAND flash, reducing transfer buffer size and optimizing system resources.
- Receiver-Managed Synchronization for Distributed Memory Latency
A receiver-managed synchronization mechanism enables scalable data access in distributed memory systems.
- Write-Same Manager Merging Logic for Memory Systems
A write-same manager merges repetitive operations by comparing logical address ranges and pattern data.
- Memory Controller Dynamic SLC MLC Mode Selection
A memory controller selects between single level cell and multi level cell modes based on data continuity patterns.
- Global Counter Implementation Using Local Caching and Delta Values
Local caching with delta values enables concurrent global counter updates, eliminating synchronization bottlenecks in multi-core systems.
- Memory Management System Predicting Access for Power Optimization
A memory management system predicts access times to activate hardware only when needed.
- GPU Cache Memory Line Segmentation for Bandwidth Reduction
A GPU architecture segments cache lines using a state bit to manage data replaceability within an n-way set associative structure.
- Memory System Open Block Recovery via Preliminary Data Copying
A memory system copies open block data to a selected block while maintaining identification information for rapid recovery.
- Processor Access Module for External Cache Control
A processor access module receives external data commands to perform cache operations without executing computing instructions.
- Flash Memory Controller L2P Address Caching via SRAM Node Index
Caching group-to-flash mapping node indexes in static random access memory reduces dynamic random access memory pressure and improves read-write response times.
- Unified AMPM Prefetch Circuit for Multi-Level Cache Control
Centralized AMPM prefetch circuit controls multi-level cache access patterns to resolve the contradiction between memory latency and energy usage.
- Storage Controller File Mapping Table Segmentation
A storage controller generates a file mapping table from command unit headers to accelerate read operations.
- Shared Memory Controller Access Key Generation
A shared memory controller generates temporal access keys to manage fine-grained read and write operations across multiple servers.
- Nonvolatile Memory Module Authentication Engine
Authentication engine generates certification values from device identifiers to prevent unauthorized access and data breaches in nonvolatile memory modules.
- Hardware Memory Migration Agent Offloads CPU Page Table Updates
A hardware memory migration agent performs page table updates and TLB flushes independently of the host processor.
- Storage Control Device Cache Block Optimization
A storage control device manages cache blocks by merging unit areas to optimize resource usage.
- Memory Tiering via Page Table and Event Sampling
A memory management apparatus combines page table access bits with processor event sampling to identify hot and cold pages for migration.
- Dynamic Behavioral Event Correlation for Cache Prediction
A behavioral event correlation system generates dynamic scores to identify relevant cache entries based on historical access patterns.
- L3 Cache Allocation for Network Slice Parallelism
A level 3 cache planning unit allocates core sets to network slices based on slice information.
- Flash Memory Controller Running Sum Data Deduplication
Calculating running sum values allows the controller to skip redundant writes, lowering the write amplifier index and improving execution efficiency.
- Cache Partitioning Controller for Multi-Owner Resource Management
Enhanced controller partitions shared data storage elements based on calculated ownership values to support flexible multi-owner access.