Disaggregated Memory Interconnect via Buffered GPIO Protocol
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Solution Overview
Problem
As computing systems become more complex, existing interconnect architectures face challenges in meeting bandwidth requirements and power efficiency, particularly in balancing performance and power consumption across different market segments, such as servers and mobile devices.
Innovation Solution
The development of a shared memory architecture that enables memory to be shared between independent nodes using load/store (LD/ST) memory semantics, facilitated by a buffered memory protocol based on a General Purpose Input/Output (GPIO) interconnect, allowing for low-latency message passing and dynamic memory allocation across nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional multi-drop buses are used for interconnect, then device complexity is reduced, but communication performance and bandwidth capability deteriorate
Solution Approach 1:
The patent segments the interconnect architecture into multiple independent point-to-point links rather than using a single shared multi-drop bus. Each node has dedicated communication paths to multiple other nodes, enabling parallel data transmission and eliminating the bandwidth bottleneck of shared buses while maintaining manageable complexity through modular link design.
Solution Approach 2:
The patent transitions from a one-dimensional shared bus architecture to a multi-dimensional mesh-like interconnect topology where multiple simultaneous communication paths exist. This dimensional expansion allows concurrent data transfers across different nodes without interference, dramatically increasing effective bandwidth while the buffered memory protocol manages the increased complexity through standardized buffering and flow control mechanisms.
2Productivity
If processing power and number of devices are increased, then computing capability is improved, but communication requirements and interconnect demand worsen
Solution Approach 1:
The buffered memory protocol implements a universal communication mechanism that handles multiple types of data transfers (memory accesses, device communication, error correction) through a single standardized interface. This multi-functional protocol reduces the need for separate specialized communication infrastructure for each function, thereby managing the complexity increase that accompanies higher computing power and device counts.
Solution Approach 2:
The patent introduces buffered memory as an intermediary layer between processing nodes and physical memory/devices. This buffer mediates communication by providing centralized coordination, flow control, and error handling, which simplifies the interconnect architecture despite the increased number of devices and communication requirements in high-performance computing systems.
3Adaptability or versatility
If existing interconnect architectures are used, then device compatibility is maintained, but power efficiency and bandwidth requirements cannot be met
Solution Approach 1:
The buffered memory protocol implements dynamic flow control and adaptive buffering that adjusts memory access patterns based on actual system demand. By dynamically managing write buffers and read requests according to real-time conditions, the system reduces unnecessary data transfers and idle processing, thereby lowering power consumption while maintaining compatibility with existing interconnect standards through configurable buffer sizes and protocol parameters.
Data Source
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AI summary
A shared memory controller receives a memory access request from a computing node, the request corresponding to a particular line of pooled memory. An error corresponding to the request is identified and the request is forwarded to a second shared memory controller in response to the error. A response is received to the request from the second shared memory controller. The response can be forwarded to the computing node by the shared memory controller.