L3 Cache Allocation for Network Slice Parallelism
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Solution Overview
Problem
Multi-core network processors face increased memory access delays and maximum access delays due to the growing number of cores, along with low network slice parallelism, which hampers efficient data exchange and resource utilization.
Innovation Solution
A cache allocation method and apparatus that involves accessing a level 3 cache upon miss responses from level 1 and level 2 caches, where the level 3 cache is shared among multiple core sets and allocates core sets to network slices based on network slice information, optimizing cache configuration and reducing access delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of cores is increased to meet data exchange and sharing requirements, then processing capability is improved, but memory access delay increases
Solution Approach 1:
The cache system is segmented into multiple levels (L1, L2, L3) with different access priorities and network slice associations. Each cache level serves specific core sets and network slices, enabling differentiated access paths that reduce overall memory access delay while maintaining multi-core processing capability.
Solution Approach 2:
The L3 cache acts as an intermediary shared by multiple core sets, mediating access between cores and external memory. The planning unit in the L3 cache coordinates access requests and allocates cache resources dynamically, reducing contention and access delay for multi-core systems.
2Device complexity
If traditional cache structures are used in multi-core systems, then implementation simplicity is maintained, but network slice parallelism remains low
Solution Approach 1:
The L3 cache planning unit performs multiple functions: it manages cache allocation, associates core sets with network slices, and dynamically configures cache resources. This multi-functional design enables the cache system to support network slice parallelism without proportionally increasing structural complexity.
Solution Approach 2:
The cache allocation structure is dynamic rather than static. The planning unit can dynamically associate different core sets with different network slices and adjust cache resource allocation based on runtime conditions, enabling flexible parallelism support while maintaining a unified cache architecture.
Data Source
AI summary
A cache allocation method is provided. A core accesses a L3 cache when detecting a miss response from each of a L1 and a L2 cache accessed by the core through sending instruction fetching instructions configured to request L1 and L2 caches to return an instruction and data. The L1 cache is a private cache of the core, the L2 cache is a common cache corresponding to a core set including the core, the L3 cache is a common cache shared by core sets, and the miss response from the L2 cache carries network slice information. A planning unit in the L3 cache allocates the core sets to network slices, configures caches for the network slices according to the network slice information, and sends a hit response to the core. The hit response is configured to return data in a cache of a network slice corresponding to the core set.