Memory Scheduler Concurrent Read Access During Data Copying

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Solution Overview

Problem

Existing computing systems face challenges in efficiently managing shared memory regions across multiple threads, particularly during data copying operations, where locking the entire critical section can lead to inefficiencies and bottlenecks, as it restricts all access during copying.

Innovation Solution

A scheduler-based approach that allows read requests from multiple threads while denying write requests to the original memory region during data copying, enabling concurrent access and improving processing capabilities by using a secondary memory region for storing copied data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the entire critical section is locked during data copying to protect data integrity, then data integrity is ensured, but access efficiency deteriorates as all thread operations are restricted

Engineering Contradiction:
Improvedata integrityVSAvoidaccess efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The critical section is segmented into multiple regions: the original memory region, a secondary memory region for copying, and a transition region. This segmentation allows different access permissions to be applied to different regions simultaneously, enabling reads from the original region while preventing writes during copying operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different access permissions are applied locally to different memory regions based on their state. The original memory region allows reads during copying, the secondary region accepts writes after copying completes, and transition regions have restricted access. This local differentiation resolves the contradiction by allowing efficient access where safe while protecting integrity where needed.

Inventive Principle:
Principle #3Local quality

2Reliability

If the entire critical section is locked during data copying to prevent concurrent writes, then data consistency is maintained, but system throughput deteriorates due to blocked read operations

Engineering Contradiction:
Improvedata consistencyVSAvoidsystem throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

A secondary memory region is pre-allocated and prepared before copying operations begin. This preliminary preparation allows the copying process to proceed without blocking read operations on the original region, as threads can continue reading from the original while data is copied to the pre-prepared secondary region.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The secondary memory region acts as an intermediary during the transition from old to new data. It receives copied data while the original region remains accessible for reads, and then becomes the new accessible region after copying completes, mediating the transition without blocking throughput.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If a scheduler is implemented to manage thread access to the critical section, then access control is improved, but device complexity increases due to additional scheduling overhead

Engineering Contradiction:
Improveaccess controlVSAvoidscheduling overhead
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The scheduler uses parameter changes in the form of access permission flags and memory region identifiers to control thread access. By changing the state parameters of memory regions (original, secondary, transition) and thread permissions (read-only, read-write, blocked), the system achieves fine-grained access control without complex scheduling logic.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10459849B1Scheduling operations in an access-controlled region of memory
Publication Date: 2019.10.29 SAS INSTITUTE INC
  • US10459849B1 patent drawing
  • US10459849B1 patent drawing
  • US10459849B1 patent drawing

AI summary

A computing device receives, at a scheduler of the computing device, a first write request from a first thread of a plurality of threads. The scheduler schedules access for the plurality of threads across a boundary of an access-controlled region in a memory of the computing device. The computing device determines that a second memory region in the access-controlled region is allocated for storing data copied from a first memory region. During copying, to the second memory region, the data copied from the first memory region, the computing device permits scheduling, by the scheduler, an operation to read from the first memory region for any read requests from the plurality of threads during the copying; and denies scheduling, by the scheduler, an operation to write to the first memory region for any subsequent write requests from the plurality of threads during the copying.