Tag Directory Aggregation for Cache Coherence

Solution Overview

Problem

Current cache coherence protocols face inefficiencies in large-scale multi-core systems, including high energy consumption and latency due to inefficient handling of multicast messages and complex acknowledgment processes, particularly in hierarchical tag directory organizations.

Innovation Solution

Implementing a non-blocking cache coherence protocol that aggregates acknowledgment messages at the tag directory and sends consolidated messages, reducing the number of messages and energy consumption, and optimizing the acknowledgment process to scale to 256 or more cores by eliminating the need for individual acknowledgments to travel long distances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If individual acknowledgment messages are sent from each processor core to the requesting core in cache coherence protocols, then cache line coherence is maintained, but network traffic and energy consumption increase significantly in large-scale multi-core systems

Engineering Contradiction:

Improvecache line coherenceVSAvoidenergy consumption

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent combines multiple individual acknowledgment messages from processor cores into a single consolidated acknowledgment message at the tag directory. Instead of each core sending separate acknowledgments back to the requesting core, the tag directory aggregates these acknowledgments and sends one consolidated message, thereby maintaining cache coherence while reducing network traffic and energy consumption.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The tag directory acts as an intermediary that receives individual acknowledgments from processor cores, aggregates them, and then sends a consolidated acknowledgment to the requesting core. This intermediary approach eliminates the need for direct individual message paths from each core to the requester, reducing overall network traffic while preserving coherence guarantees.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If individual acknowledgment messages are sent from each processor core to the requesting core, then cache line coherence is maintained, but transaction latency increases due to the large number of messages traveling long distances

Engineering Contradiction:

Improvecache line coherenceVSAvoidtransaction latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent combines multiple individual acknowledgment messages from processor cores into a single consolidated acknowledgment message at the tag directory. Instead of each core sending separate acknowledgments back to the requesting core, the tag directory aggregates these acknowledgments and sends one consolidated message, thereby maintaining cache coherence while reducing network traffic and energy consumption.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The tag directory acts as an intermediary that receives individual acknowledgments from processor cores, aggregates them, and then sends a consolidated acknowledgment to the requesting core. This intermediary approach eliminates the need for direct individual message paths from each core to the requester, reducing overall network traffic while preserving coherence guarantees.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If traditional cache coherence protocols are used in large-scale multi-core systems, then cache line coherence is maintained, but the system scales poorly due to the large number of messages required

Engineering Contradiction:

Improvecache line coherenceVSAvoidsystem scalability

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent combines multiple individual acknowledgment messages from processor cores into a single consolidated acknowledgment message at the tag directory. Instead of each core sending separate acknowledgments back to the requesting core, the tag directory aggregates these acknowledgments and sends one consolidated message, thereby maintaining cache coherence while reducing network traffic and energy consumption.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The tag directory serves multiple functions: it manages cache line coherence, tracks which cores have copies of cache lines, aggregates acknowledgment messages, and determines when coherence updates are complete. This multi-functional approach enables the system to scale to 256 or more cores by consolidating coordination tasks at the tag directory rather than requiring complex point-to-point communication between all cores.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9740617B2Hardware apparatuses and methods to control cache line coherence

Publication Date: 2017.08.22 INTEL CORP

AI summary

Methods and apparatuses to control cache line coherence are described. A hardware processor may include a first processor core with a cache to store a cache line, a second set of processor cores that each include a cache to store a copy of the cache line, and cache coherence logic to aggregate in a tag directory an acknowledgment message from each of the second set of processor cores in response to a request from the first processor core to modify the copy of the cache line in each of the second set of processor cores and send a consolidated acknowledgment message to the first processor core.