Hardware Memory Migration Agent Offloads CPU Page Table Updates

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Solution Overview

Problem

The current data migration process in computing systems, which involves CPU-intensive operations like memory access and address translation updates, burdens the central processing unit (CPU) and diverts resources from more time-sensitive tasks, especially when repeated for ensuring data synchronization and updating page tables and TLBs.

Innovation Solution

An integrated circuit configured as a hardware memory migration agent offloads data migration tasks from the CPU, utilizing a request parser, copy operation manager, page table manager, TLB manager, and controller to perform memory access, update address translations, and flush TLBs asynchronously, thereby reducing CPU load and optimizing resource utilization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data migration is performed by CPU execution of software instructions, then data migration functionality is achieved, but CPU resources are significantly burdened and diverted from other computing tasks

Engineering Contradiction:
Improvedata migration throughputVSAvoidCPU availability for other tasks
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent extracts the data migration function from the CPU by implementing a dedicated hardware memory migration agent. This separate hardware component handles memory access operations, page table updates, and TLB flush operations independently, removing the burden from the CPU and allowing it to focus on other computing tasks without sacrificing data migration capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The hardware memory migration agent acts as an intermediary between the CPU and memory systems. It receives migration requests from the CPU, performs the actual data migration operations including memory access and address translation updates, and notifies the CPU when migration is complete. This intermediary approach allows the CPU to initiate and monitor migration without being actively involved in the time-consuming operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If CPU performs memory access operations and address translation updates during data migration, then data migration is completed, but computing resources needed for other computing tasks are consumed

Engineering Contradiction:
Improvedata migration completenessVSAvoidoverall system throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the resource-intensive memory access operations, page table updates, and TLB flush operations from the CPU and implements them in dedicated hardware. This ensures that data migration completeness is maintained through proper hardware-managed operations while preventing these operations from consuming CPU resources needed for other computing tasks.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The hardware memory migration agent performs self-service by autonomously handling memory access operations, updating page tables, and flushing TLBs without requiring continuous CPU intervention. The agent independently manages the entire migration process and only interacts with the CPU at the beginning (receiving requests) and end (notifying completion), allowing the system to maintain both migration reliability and overall productivity.

Inventive Principle:
Principle #25Self-service

3Reliability

If CPU is used for repeated data synchronization operations, then data consistency is ensured, but CPU load increases and resources are diverted from time-sensitive tasks

Engineering Contradiction:
Improvedata synchronization accuracyVSAvoidCPU availability
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent extracts repeated data synchronization operations from the CPU and implements them in hardware. The memory migration agent automatically handles synchronization by updating page tables and flushing TLBs during migration, ensuring data consistency without requiring CPU involvement in each synchronization operation. This maintains reliability while preserving CPU availability for time-sensitive tasks.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11620233B1Memory data migration hardware
Publication Date: 2023.04.04 AMAZON TECH INC
  • US11620233B1 patent drawing
  • US11620233B1 patent drawing
  • US11620233B1 patent drawing

AI summary

An integrated circuit for offloading a page migration operation from a host processor is provided. The integrated circuit is configured to: receive, from the host processor, a request to perform the page migration operation from a first physical address to a second physical address; and based on the request, perform the page migration operation. The page migration operation comprises: performing a copy operation of data from the first physical address to the second physical address, and updating a page table entry based on the second physical address, to enable the host processor to access the data from the second physical address based on the updated page table entry.