Memory Bank Access via Mapping Function for Concurrent Masters
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Solution Overview
Problem
Conventional data storage systems face challenges in increasing throughput and reducing latency while maintaining low power consumption and cost, as they often require increased power and cost due to wider data paths and higher clock rates to manage concurrent access by multiple masters to single port memory banks.
Innovation Solution
The system employs a method where multiple masters concurrently access different physical memory banks using a mapping function that spreads access across banks, allowing each master to access a memory bank with a high probability without collisions, thereby increasing throughput and reducing latency while maintaining low power consumption and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple masters concurrently access single port memory banks using conventional methods, then throughput increases, but power consumption and cost increase due to wider data paths and higher clock rates
Solution Approach 1:
The memory system is segmented into multiple independent memory banks, each capable of handling access requests separately. By distributing concurrent access requests across multiple banks, the system achieves parallelism without requiring wider data paths or higher clock rates within each bank, thus maintaining low power consumption while increasing overall throughput.
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing memory into multiple banks that can be accessed concurrently. Instead of increasing bandwidth within a single memory bank (which would require wider data paths and higher power), the system adds temporal and spatial parallelism across multiple banks, achieving higher throughput without proportionally increasing power consumption.
2Productivity
If multiple masters concurrently access single port memory banks using conventional methods, then throughput increases, but cost increases due to wider data paths and higher clock rates
Solution Approach 1:
The memory system is segmented into multiple independent memory banks, each capable of handling access requests separately. By distributing concurrent access requests across multiple banks, the system achieves parallelism without requiring wider data paths or higher clock rates within each bank, thus maintaining low power consumption while increasing overall throughput.
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing memory into multiple banks that can be accessed concurrently. Instead of increasing bandwidth within a single memory bank (which would require wider data paths and higher power), the system adds temporal and spatial parallelism across multiple banks, achieving higher throughput without proportionally increasing power consumption.
3Speed
If multiple masters access the same memory bank concurrently, then access speed increases, but collision probability increases reducing successful access rate
Solution Approach 1:
The memory system is segmented into multiple independent memory banks, each capable of handling access requests separately. By distributing concurrent access requests across multiple banks, the system achieves parallelism without requiring wider data paths or higher clock rates within each bank, thus maintaining low power consumption while increasing overall throughput.
Data Source
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AI summary
A first master receives a first virtual address in a virtual memory, the first virtual address m the virtual memory corresponding, according to a mapping function, to a first physical address of a first physical memory bank which is to be accessed by the first master. The first master accesses the first physical address to perform a first memory' operation in the first memory' bank. A second master receives a second virtual address in a virtual memory, the second virtual address m the virtual memory corresponding, according to the mapping function, to a second physical address of a second physical memory bank which is to be accessed by the second master. Concurrently with access by the first master to the first physical address, the second master accesses the second physical address to perform a second memory operation in the second physical memory bank.