Cache Dirty Line Management for Power Failure Data Loss

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In memory systems, the speed difference between the host and memory leads to inefficiencies, particularly during sudden power-off events, where dirty lines in the cache memory may not be consistently written to main memory, requiring effective management of dirty lines to prevent data loss.

Innovation Solution

A cache system with a dirty line list and a cache controller that stores the least-recently-used dirty line in the lowest-order node and forcibly evicts it when an overflow occurs, shifting status information to maintain a predetermined number of dirty lines, ensuring data consistency during power interruptions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of dirty lines in cache memory increases to improve data storage capacity, then more data can be cached, but the complexity of managing dirty lines increases and data loss risk during power failures worsens

Engineering Contradiction:
Improvenumber of dirty linesVSAvoidcomplexity of managing dirty lines
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The dirty line list is segmented into multiple nodes (first node, second node, third node, etc.) arranged in a specific order. Each node stores status information of a dirty line, allowing the system to manage a large number of dirty lines through structured segmentation rather than unmanaged accumulation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system pre-establishes a dirty line list with multiple nodes before overflow occurs. When overflow is detected, the system has pre-defined eviction paths (evicting from first node to second node, etc.) ready to execute immediately, avoiding complex real-time decision-making during critical power failure scenarios

Inventive Principle:
Principle #10Preliminary action

2Reliability

If all dirty lines are written to main memory immediately to prevent data loss, then data consistency is improved, but the time required for caching operations increases

Engineering Contradiction:
Improvedata consistencyVSAvoidcaching operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Instead of writing all dirty lines to main memory immediately, the system performs partial writes based on priority. The dirty line list structure enables selective eviction where only certain dirty lines (those in earlier nodes) are prioritized for writing to main memory, allowing caching operations to proceed faster while still maintaining data consistency for critical data

Inventive Principle:
Principle #16Partial or excessive action

3Device complexity

If a simple eviction policy is used to reduce management overhead, then device complexity is reduced, but the precision of dirty line management deteriorates

Engineering Contradiction:
Improvemanagement overheadVSAvoidprecision of dirty line management
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The dirty line list employs a dynamic ordered structure where nodes can be selectively evicted based on their position in the list. The system dynamically adjusts which dirty lines to evict (prioritizing those in first nodes over later nodes) without requiring complex real-time analysis, achieving precise management through structured dynamics rather than simple static policies

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11593276B2Data caching methods of cache systems
Publication Date: 2023.02.28 SK HYNIX INC
  • US11593276B2 patent drawing
  • US11593276B2 patent drawing
  • US11593276B2 patent drawing

AI summary

A cache system includes a cache memory having a plurality of blocks, a dirty line list storing status information of a predetermined number of dirty lines among dirty lines in the plurality of blocks, and a cache controller controlling a data caching operation of the cache memory and providing statuses and variation of statuses of the dirty lines, according to the data caching operation, to the dirty line list. The cache controller performs a control operation to always store status information of a least-recently-used (LRU) dirty line into a predetermined storage location of the dirty line list.