DRAM Scrambling Circuitry for Data Security Without Speed Penalty
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Solution Overview
Problem
Current methods for enhancing data security in Dynamic Random Access Memory (DRAM) are inefficient, as encrypting data is too resource-intensive for main memory systems, and existing solutions do not effectively protect data from unauthorized access, especially when DIMMs are removed and cooled.
Innovation Solution
A method and system that utilize a memory controller to select Error Correction Code (ECC) strength based on data importance, scramble data bits and bank select bits, and use volatile registers to store scrambling information, ensuring data security without altering mainline read and write operations, and rearranging data to maintain security levels proportional to user requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is encrypted in DRAM, then data security is improved, but access speed and system performance deteriorate due to overhead
Solution Approach 1:
The patent extracts the encryption/decryption function from the main memory access path by implementing it in the memory controller rather than in the DRAM array itself. This separation allows the encryption operations to be performed on data as it passes through the controller without requiring modifications to the fast DRAM access path, thus maintaining access speed while providing security.
Solution Approach 2:
The memory controller acts as an intermediary between the system and the DRAM array, performing encryption on write operations and decryption on read operations. This intermediary approach allows security to be layered onto the existing memory subsystem without disrupting the high-speed access characteristics of DRAM, as the encryption/decryption occurs at the controller level rather than within the memory array.
2Reliability
If scrambling circuitry and registers are added to DRAM, then data security is improved, but device complexity increases
Solution Approach 1:
The patent merges the scrambling functionality into the existing memory controller architecture, combining it with other control functions rather than adding a separate, standalone encryption device. The mode register set and scrambling circuitry are integrated into the controller's existing structure, allowing security features to be added without proportionally increasing overall system complexity.
Solution Approach 2:
The memory controller is designed to perform multiple functions including traditional memory control, error correction, and now scrambling/encryption operations. By making the controller universal and multi-functional, the patent avoids adding dedicated separate hardware for each function, thereby improving security while minimizing the increase in device complexity through shared resources and integrated design.
3Loss of energy
If volatile registers store scrambling information, then power consumption is reduced, but data security is compromised when power is lost
Solution Approach 1:
The patent employs volatile registers that discard scrambling information when power is lost, and the system recovers the original scrambling keys from secure storage (such as fuses or secure memory regions) when power is restored. This approach minimizes power consumption by not maintaining scrambling keys in non-volatile form during operation, while still ensuring security is restored after power loss through the recovery mechanism.
Solution Approach 2:
The patent changes the state of the scrambling keys from persistent (non-volatile) to transient (volatile) during powered operation, reducing power consumption. When power is lost, the system transitions back to the original secure storage state, retrieving the keys when needed. This parameter change between volatile and non-volatile storage modes allows the system to balance power consumption and security requirements dynamically.
Data Source
AI summary
A method, system and memory controller for implementing enhanced security in a memory subsystem including DRAM in a computer system. A memory includes a register to hold scrambling information transmitted from a memory controller; and scrambling circuitry on the memory to scramble at least one of bank select bits and data bits responsive to the scrambling information in the register.