PCM Memory Protection via Ternary Codeword Selection
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Solution Overview
Problem
Deeply scaled Phase Change Memory (PCM) is susceptible to malicious write attacks due to heat-induced write disturbance errors, which can corrupt data by resetting neighboring cells, especially in compact memory designs beyond 20 nm technology.
Innovation Solution
The method involves dividing a cacheline into sub-blocks, generating and selecting ternary codewords using Canonical Sign Digit (CSD) encoding to minimize the likelihood of inter-word line write disturbance errors, thereby reducing the impact of heat from resetting cells on neighboring cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If PCM memory cells are compacted to increase memory capacity, then memory capacity and scalability are improved, but susceptibility to write attacks and write disturbance errors increases
Solution Approach 1:
The memory system is segmented into multiple banks, and each bank is further divided into sub-blocks. This segmentation allows the memory to isolate write disturbance effects to specific sub-blocks, preventing propagation to the entire memory array. The selective refresh operation can then be applied to only the affected sub-blocks rather than the entire bank, maintaining reliability while supporting high capacity.
Solution Approach 2:
The system performs preliminary detection of write disturbance errors by monitoring write operations and identifying potential victim cells before actual data corruption occurs. Once a vulnerable sub-block is identified, a selective refresh operation is proactively applied to restore the cells to their correct state, preventing data corruption before it happens.
2Object-affected harmful factors
If rowhammer attacks are performed to reset cells, then malicious write attacks can corrupt data, but the heat from resetting cells disturbs resistance states of neighboring cells
Solution Approach 1:
The system converts the harmful heat effect into a beneficial detection mechanism. By monitoring for write disturbance errors that occur naturally due to heat from reset operations, the system can identify vulnerable sub-blocks and apply selective refresh operations. The harmful thermal effect becomes a signal for proactive error prevention.
Solution Approach 2:
The system implements feedback by continuously monitoring memory operations and detecting write disturbance errors. When errors are detected in specific sub-blocks, the system responds by applying selective refresh operations to those sub-blocks. This closed-loop feedback mechanism dynamically adapts to thermal conditions and prevents data corruption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates write disturbance errors in PCM memory, preserving system performance by ensuring that only cells in the SET state are disturbed, thus preventing data corruption and enhancing security against malicious attacks.
Implementation Method 1
the heat resulting from resetting PCM cells disturbs the resistance states of neighboring cells
Data Source
AI summary
A method and apparatus of protecting a memory from a write attack includes dividing a cacheline of memory into a plurality of sub-blocks. A codeword is generated from at least one sub-block of the plurality of sub-blocks and a complement of the at least one sub-block. One of the generated codewords is selected, wherein the selected codeword is used for storage in memory.