Memory Marking for Address Translation Structures

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In computing environments with virtualization technology, the latency for rebuilding translation look-aside buffer (TLB) entries increases when memory backing address translation tables is paged out, and the hypervisor lacks intelligence in paging decisions due to unawareness of which pages back address translation tables, leading to inefficient memory management.

Innovation Solution

A computer program product that initiates marking of memory blocks to indicate whether they back address translation structures, using instructions like Extract And Set Storage Attributes (ESSA) to specify this information, allowing the virtual machine manager to make informed paging decisions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory backing address translation tables is paged out to storage medium, then memory management flexibility is improved, but latency for rebuilding TLB entries increases

Engineering Contradiction:

Improvememory management flexibilityVSAvoidlatency for rebuilding TLB entries

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by marking memory pages as backing address translation structures before paging decisions are made. This advance classification allows the hypervisor to proactively identify and protect critical pages from being paged out, preventing the need to rebuild TLB entries later and thus reducing the latency penalty.

Inventive Principle:

Principle #10Preliminary action

2Extent of automation

If hypervisor makes paging decisions without knowledge of address translation table pages, then paging autonomy is maintained, but paging decision intelligence deteriorates

Engineering Contradiction:

Improvepaging autonomyVSAvoidpaging decision intelligence

Core Design Contradiction:

Extent of automationVSLoss of information

Solution Approach 1:

The patent implements feedback by having the control program provide information about which memory pages back address translation structures to the hypervisor through marking mechanisms. This feedback loop enables the hypervisor to make informed paging decisions while maintaining its autonomy, as it now has visibility into which pages are critical for address translation without losing its decision-making independence.

Inventive Principle:

Principle #23Feedback

3Productivity

If operating system determines page reuse frequency, then paging optimization capability is improved, but system complexity increases

Engineering Contradiction:

Improvepaging optimization capabilityVSAvoidsystem complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies the extraction principle by removing the complex task of determining page reuse frequency from the operating system and consolidating it into the control program. The control program, which already has visibility into address translation structure pages through marking, now handles the intelligence for paging decisions, simplifying the overall system architecture while maintaining paging optimization capability.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS10802986B2Marking to indicate memory used to back address translation structures

Publication Date: 2020.10.13 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A marking capability is used to provide an indication of whether a block of memory is backing an address translation structure of a control program being managed by a virtual machine manager. By providing the marking, the virtual machine manager may check the indication prior to making paging decisions. With this information, a hint may be provided to the hardware to be used in decisions relating to purging associated address translation structures, such as translation look-aside buffer (TLB) entries.