Cache Data Exchange Method Reducing Bus Overhead

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Solution Overview

Problem

In symmetric multiprocessing (SMP) systems, the inefficiency of atomic compare operations leads to unnecessary data invalidation and re-access to memory when data comparison fails, reducing processing performance due to increased bus bandwidth overhead and chip power consumption.

Innovation Solution

A data processing method that includes comparing target data before initiating data snooping on other cache units, ensuring data is not invalidated until comparison succeeds, thereby reducing bus bandwidth overhead and chip power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data snooping is initiated without comparing target data first, then data invalidation occurs quickly, but unnecessary data invalidation and re-access to memory increases bus bandwidth overhead and chip power consumption

Engineering Contradiction:
Improvedata invalidation speedVSAvoidbus bandwidth overhead and chip power consumption
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent applies preliminary action by comparing target data with the second cache unit's data before initiating data snooping. This preliminary comparison prevents unnecessary data invalidation when data changes are not detected, thereby reducing bus bandwidth overhead and chip power consumption while maintaining fast invalidation speed when changes are actual.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If data snooping is initiated without comparison, then cache coherence is maintained, but processing performance decreases due to unnecessary re-access to memory

Engineering Contradiction:
Improvecache coherenceVSAvoidprocessing performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces an intermediary comparison step between the target data and the second cache unit's data before proceeding with data snooping. This intermediary mechanism acts as a filter that prevents unnecessary cache invalidation and memory re-access, thereby maintaining cache coherence while improving processing performance by avoiding redundant operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If atomic compare operations are performed without preliminary data comparison, then atomicity is ensured, but processing efficiency decreases due to increased overhead

Engineering Contradiction:
Improveatomic operation correctnessVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by performing a data comparison before initiating the atomic compare operation and data snooping sequence. This preliminary check ensures atomicity is maintained while improving processing efficiency by avoiding unnecessary atomic operation execution when no data changes are detected, thereby reducing overall operational overhead.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4730130A1Data processing method, data processing apparatus, data processing system, and readable medium
Publication Date: 2026.04.22 SANECHIPS TECH CO LTD
  • EP4730130A1 patent drawingFigure 1~2
  • EP4730130A1 patent drawingFigure 3~4
  • EP4730130A1 patent drawingFigure 5~6

AI summary

Provided in the present disclosure is a data processing method applied to a data processing apparatus in a data processing system. The method comprises: when a data exchange request message sent by a first cache unit is received, acquiring address information carried in the data exchange request, and determining first target data corresponding to address information in a memory; sending a notification message to the first cache unit; receiving second target data and third data which are sent by the first cache unit, wherein the third data is data that is to be subjected to data exchange with the first target data, and the second target data is data that a second cache unit has requested to read; and when the second target data is not equal to the first target data, returning, to the first cache unit, a data exchange response message that carries the third data.