Memory Tiering via Page Table and Event Sampling
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Solution Overview
Problem
Current memory tiering systems in computer systems are inefficient due to reliance on page table A/D bits alone for determining hot and cold pages, which does not account for cache residency, leading to suboptimal data movement and performance issues, especially with large pages that are sparsely accessed.
Innovation Solution
Combining page table A/D bit tracking with processor event-based sampling to gather memory access data, allowing for more accurate identification of hot and cold pages and their cache residency, thereby optimizing page migration between faster and slower memory tiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If page table A/D bits alone are used for determining hot and cold pages, then the method is simple, but the accuracy of hot/cold page identification is poor
Solution Approach 1:
The patent combines page table A/D bit tracking with processor event-based sampling to gather memory access data. This merging of two different data collection mechanisms provides both the simplicity of page table tracking and the precision of event-based sampling, resolving the contradiction between method simplicity and identification accuracy.
Solution Approach 2:
The patent introduces an intermediary mechanism that collects memory access data from both page tables and processor events, then uses this combined data to determine hot and cold pages. This intermediary approach allows the system to leverage multiple data sources without directly implementing complex analysis in the memory management unit.
2Quantity of substance
If memory tiering is implemented with multiple memory types, then capacity and cost-effectiveness are improved, but data movement efficiency deteriorates
Solution Approach 1:
The patent performs preliminary identification of hot and cold pages using combined page table and event-based data before executing data movement operations. This preliminary classification allows the memory management unit to make more informed decisions about which pages to migrate between memory tiers, improving data movement efficiency.
Solution Approach 2:
The patent uses processor event-based sampling to continuously monitor memory access patterns and provides feedback to the memory management unit. This feedback mechanism enables dynamic adjustment of page migration decisions based on actual access behavior, optimizing data movement efficiency in multi-tier memory systems.
3Quantity of substance
If large pages are used to increase memory capacity, then memory capacity is improved, but access precision deteriorates due to sparse accesses
Solution Approach 1:
The patent applies partial action by using processor event-based sampling to focus analysis on actually accessed portions of large pages. Instead of treating entire large pages uniformly, the system identifies and analyzes specific accessed regions, allowing for more precise hot/cold page determination even within large pages that have sparse access patterns.
Data Source
AI summary
Examples relate to an apparatus, a device, a method, and computer program for managing memory of a computer system, and to a computer system comprising such an apparatus or device. The apparatus is configured to obtain first information on accesses to at least one of a first tier of memory and a second tier of memory within a memory hierarchy of the computer system from a page table, the first and second tiers of memory being below the processor cache tiers of the memory hierarchy, the first tier of memory having a higher memory performance than the second tier of memory. The apparatus is configured to obtain second information on accesses to at least one of the first tier of memory and the second tier of memory from logged processor events related to the accesses to the first tier of memory and the second tier of memory. The apparatus is configured to select one or more memory pages to be moved between the first tier of memory and the second tier of memory based on the first and second information on the accesses to at least one of the first tier of memory and the second tier of memory.