Multi-Level NVM Read Time Consistency via Voltage Level Comparison
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multi-level NAND-type flash memory systems face challenges due to variability in read times across different bits per cell, leading to inefficiencies in device performance and resource allocation, particularly in garbage collection and multi-threaded operations.
Innovation Solution
An enhanced encoding scheme is implemented to achieve consistent read times across all bits in multi-level non-volatile memory structures by modifying the number of voltage level comparisons for each bit, allowing for similar read times across all pages, thereby optimizing system resources and reducing the size of transfer buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level NAND memory uses more voltage levels to increase bits per cell, then storage capacity increases, but read time variability increases
Solution Approach 1:
The patent changes the parameter of voltage level comparison count for different bits. Specifically, it assigns different numbers of voltage level comparisons to different bits (e.g., first bit uses 3 comparisons, second bit uses 2 comparisons, third bit uses 1 comparison) to balance the total read time across all bits, thereby reducing read time variability while maintaining high storage capacity
Solution Approach 2:
The patent implements dynamic read time balancing by adjusting the number of voltage level comparisons based on the specific bit being read. The system dynamically selects comparison schemes to ensure that each bit takes approximately the same time to read, transforming a static uniform comparison approach into a dynamic adaptive one
2Loss of time
If transfer buffer size is increased to support longest read times, then read time variability is accommodated, but device cost and performance deteriorate
Solution Approach 1:
By changing the parameter of voltage level comparison counts, the patent achieves uniform read times across all bits. This eliminates the need for large transfer buffers to accommodate variable read times, thereby reducing device complexity and cost while maintaining time variability accommodation
3Quantity of substance
If more voltage level comparisons are conducted for certain bits, then storage capacity increases, but comparison circuitry size increases
Solution Approach 1:
The patent optimizes the parameter distribution of voltage level comparisons across different bits. By assigning fewer comparisons to later bits (e.g., third bit uses only 1 comparison) and compensating with parallel processing or optimized sequencing, the total comparison circuitry volume is reduced while maintaining multi-level storage capacity
Data Source
AI summary
Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.