Microprocessor Load Queue Using Physical Address Proxies
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Solution Overview
Problem
Cache memories in microprocessors face challenges in reducing access time and improving cache coherency, particularly in multi-processor systems, where the overhead of cache coherence protocols and the storage of additional information hinder performance.
Innovation Solution
A microprocessor design incorporating a first-level cache and a second-level set associative cache with a load queue that uses physical address proxies (PAPs) to manage cache entries, enabling efficient cache coherence and reducing the need for full physical addresses, thereby improving access times and cache capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache memories store full physical addresses to ensure cache coherency, then cache coherency is maintained, but cache capacity and access speed are reduced due to storing additional information
Solution Approach 1:
The patent extracts only the necessary portion of the physical address (set index and way fields) to create a compressed proxy representation. This allows the cache to track address mappings for coherency without storing complete physical addresses, thereby freeing up cache capacity while maintaining coherency tracking capability.
Solution Approach 2:
The patent changes the representation parameter from full physical addresses to compressed proxies containing only set index and way fields. This parameter transformation reduces the storage requirements for address tracking information, enabling increased cache capacity while preserving the ability to maintain cache coherency.
2Reliability
If cache memories store full physical addresses for coherency protocols, then cache coherency is maintained, but cache access time increases due to additional information storage requirements
Solution Approach 1:
The patent extracts only the essential address components (set index and way) needed for coherency tracking, creating a compact proxy representation. This reduction in stored information decreases the time required to process and compare address mappings during cache access operations while maintaining coherency assurance.
Solution Approach 2:
The patent transforms the address storage parameter from full physical addresses to compressed proxies with fewer fields. This parameter change reduces the computational overhead and storage access time associated with maintaining cache coherency, thereby speeding up cache operations.
3Reliability
If cache memories allocate more space for address tracking information, then cache coherency is improved, but physical cache size increases
Solution Approach 1:
The patent extracts only the minimal necessary address fields (set index and way) to create a compressed proxy representation. This extraction approach reduces the space required for address tracking information within the cache, allowing more physical space to be allocated to actual data storage while maintaining coherency tracking capability.
Solution Approach 2:
The patent changes the address representation parameter from full physical addresses to compressed proxies containing only essential fields. This parameter transformation significantly reduces the storage footprint of address tracking information, enabling increased physical cache capacity for data storage while preserving coherency management functionality.
Data Source
AI summary
A L2 set associative cache that is inclusive of an L1 cache. Each entry of a load queue holds a load physical address proxy (PAP) for a load physical memory line address (PMLA) rather than the load PMLA itself. The load PAP comprises the set index and the way that uniquely identifies the L2 entry that holds a memory line specified by the load PMLA. Each load queue entry indicates whether the load instruction has completed execution. The microprocessor removes a memory line at a removal PMLA from an L2 entry and forms a removal PAP as a proxy for the removal PMLA. The removal PAP comprises a set index and a way that uniquely identifies the removed entry. The microprocessor snoops the load queue with the removal PAP to determine whether the removal PAP matches one or more load PAPs in one or more load queue entries associated with one or more load instructions that have completed execution and, if so, signals an abort request.