Flash Memory Controller Sequencer Reduces CPU Occupancy
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Solution Overview
Problem
Conventional semiconductor memory systems experience poor access performance due to the dominant CPU occupancy time required to set registers for multiple sequences in flash memory access, leading to prolonged access times from command input to memory access completion.
Innovation Solution
A controller with an instruction table memory storing coded sequences, a program counter, a decoder, and an executing unit that decodes and executes access to nonvolatile semiconductor memory, reducing CPU involvement by pre-coding command sequences and using a hardware sequencer for direct memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the CPU sets registers in accordance with various command sequences to access flash memory, then the flash memory can be accessed with different command sequences, but the CPU occupancy time becomes dominant and access performance becomes poor
Solution Approach 1:
The patent introduces a sequencer as an intermediary component between the CPU and flash memory. The sequencer contains a sequence register that stores command sequences and automatically executes them, mediating the interaction between the CPU and flash memory. This allows the CPU to issue commands without manually setting registers for each access operation, thereby improving access performance while maintaining command sequence flexibility.
Solution Approach 2:
The sequencer is designed to automatically execute stored command sequences without requiring continuous CPU intervention. Once the CPU loads a command sequence into the sequence register, the sequencer independently manages the flash memory access operations, making the system self-sufficient for routine access operations and reducing CPU occupancy time.
2Reliability
If the CPU sets registers for each flash memory access, then the access can be controlled precisely, but the time from command input to access completion becomes long
Solution Approach 1:
The patent implements preliminary action by pre-storing command sequences in the sequence register of the sequencer. Instead of setting registers in real-time during each access operation, the CPU prepares and loads the complete command sequence in advance. This preliminary preparation enables the sequencer to execute accesses automatically without delays, reducing the time from command input to access completion while maintaining precise control.
3Ease of operation
If the CPU is set in standby state to wait for next command, then the system can respond to host apparatus, but the CPU occupancy time increases and power consumption rises
Solution Approach 1:
The sequencer takes over the task of handling flash memory access operations, enabling the CPU to exit standby mode more quickly. After issuing a command to the sequencer, the CPU can immediately return to handling host apparatus communications without remaining in a prolonged standby state. This division of labor reduces overall CPU occupancy time and associated power consumption while maintaining full host communication capability.
Data Source
AI summary
A controller includes an instruction table memory, a program counter, a first decoder, and a first executing unit. The instruction table memory stores an instruction code obtained by coding a sequence to access a nonvolatile semiconductor memory. A read address in the instruction table memory is set to the program counter. The first decoder decodes the instruction code read from the instruction table memory to output a first decode signal. The first executing unit executes access to the nonvolatile semiconductor memory on the basis of the first decode signal output from the first decoder.