Memory Allocator LLC Slice Mapping for CPU Cores
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Solution Overview
Problem
Existing memory management systems do not efficiently allocate memory to applications based on the hierarchical memory system of CPUs, leading to suboptimal performance and increased power consumption due to inefficient data access times across different memory levels.
Innovation Solution
A method and memory allocator that dynamically allocate memory by determining if requested memory is available in a faster memory unit and mapping it to the appropriate Last Level Cache (LLC) slice associated with the CPU core, thereby optimizing data access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory is allocated without considering LLC slice mapping, then memory allocation is simple and fast, but data access latency increases and performance decreases
Solution Approach 1:
The memory allocator performs preliminary actions by determining LLC slice mappings for candidate memory regions before final allocation. This advance planning ensures that allocated memory is optimally mapped to LLC slices, reducing subsequent data access latency without requiring complex runtime decisions.
Solution Approach 2:
The patent replaces the traditional hash function-based memory-to-LLC mapping mechanism with a system that uses predetermined mappings between memory regions and LLC slices. This substitution allows the allocator to make informed decisions about memory allocation based on known mapping relationships, improving performance while managing complexity.
2Speed
If data is fetched from slower memory levels, then memory capacity is sufficient, but data access time increases significantly
Solution Approach 1:
The patent applies local quality by creating specific mappings between certain memory regions and corresponding LLC slices. Instead of uniform memory allocation, the system ensures that frequently accessed data resides in memory regions that are locally optimized for fast access to specific CPU cores, thereby improving data access speed while maintaining overall memory capacity.
3Use of energy by moving object
If memory allocation ignores CPU core-LLC slice association, then allocation is simpler, but power consumption increases due to inefficient access patterns
Solution Approach 1:
The patent replaces the conventional memory allocation mechanism that ignores CPU-LLC relationships with a new system that incorporates predetermined mappings between memory regions and LLC slices. This substitution enables the allocator to make energy-efficient decisions by directing memory allocations to regions optimally associated with the executing CPU core, reducing power consumption while managing allocation complexity.
Data Source
AI summary
A memory allocator in a computer system comprising a plurality of CPU cores (5101-5104) and a first (530) and a second (5120) memory unit having different data access times and wherein each one of the first and the second memory units is divided into memory portions wherein each memory portion (SLICE 0-3) in the second memory unit is associated with at least one memory portion (A-G) in the first memory unit, and wherein each memory portion in the second memory unit is associated with a CPU core. If at least a predetermined number of memory portions in the first memory unit being part of the available requested memory is associated with the memory portion in the second memory unit that is associated with the CPU core on which the requesting application is running, the requested available memory is allocated to the requesting application.