Big Core Activation via Instruction Splitting and Parallel Execution
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Solution Overview
Problem
Existing computing systems face challenges in efficiently executing large instructions across multiple processing devices, as they often require separate configurations for each architecture, leading to difficulties in handling instructions beyond the capabilities of individual processing units.
Innovation Solution
A software and/or firmware-based application programming interface (API) is introduced to process instructions from applications and instruct microcode to configure processing units to execute instructions, regardless of their structure. This API determines if and how to execute instructions by combining the capabilities of multiple processing units, effectively creating a conditionally activated big core.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate configurations are used for each processing device architecture, then each device can execute its native instructions efficiently, but the system cannot handle instructions beyond the capabilities of individual processing units
Solution Approach 1:
The patent divides a large instruction that exceeds the capability of a single processing device into multiple sub-instructions. Each sub-instruction is then executed by a different processing device (big core or small device processor), and the results are combined to produce the final output. This segmentation allows the system to handle instructions beyond what any single device could process alone.
2Power
If big device processors are used to handle high performance applications, then computational power is improved, but power consumption and device footprint increase
Solution Approach 1:
The patent implements dynamic instruction routing where the system evaluates each incoming instruction and determines whether it can be executed by a small device processor or if it requires a big device processor. This dynamic approach allows the system to use high-performance big cores only when necessary, rather than always operating at high power consumption levels, thus optimizing the balance between computational power and energy efficiency.
3Productivity
If multiple processing devices are combined to execute large instructions, then the system can handle complex computations, but coordination and instruction splitting become more complex
Solution Approach 1:
The patent introduces an intermediary component that acts as a mediator between the incoming instruction and the multiple processing devices. This intermediary analyzes the instruction, determines the appropriate splitting strategy, assigns sub-instructions to suitable processing devices (big cores or small device processors), and coordinates the combination of results. This intermediary layer simplifies the overall system architecture by centralizing the complex coordination logic.
Data Source
AI summary
Methods, apparatus, and articles of manufacture to conditionally activate a big core in a computing system are disclosed. An example apparatus including instructions stored in the apparatus; and processor circuitry to execute the instructions to: in response to a request to operate two or more processing devices as a single processing device, determine whether the two or more processing devices are available and capable of executing instructions according to the request; when the two or more processing devices are available and capable: split the instructions into first sub-instructions and second sub-instructions; provide (a) the first sub-instructions to a first processing device of the two or more processing devices and (b) the second sub-instructions to a second processing device of the two or more processing devices; and generate an output by combining a first output of the first processing device and a second output of the second processing device.