Big Via Bonding Pad for CMOS Image Sensor Peeling
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating bonding pads for CMOS image sensors, particularly with thin metal layers, as they often exhibit peeling or defects due to insufficient size and strength, leading to issues like wire bond non-stack on pad, peeling, and interlayer dielectric cracking.
Innovation Solution
The solution involves forming a 'big via' in the bonding pad region with a significantly larger dimension compared to the non-bonding pad region, which enhances mechanical support and contact area, preventing peeling and cracking, and allowing secure wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If thin metal layers are used in CMOS image sensors, then the device complexity and geometry size are reduced, but the bonding pads exhibit peeling or other defects due to insufficient size and strength
Solution Approach 1:
The bonding pad structure is segmented into multiple layers: a thin AlCu metal layer for device functionality and a thicker underlying metal layer (such as tungsten or copper) for mechanical support. This segmentation allows each layer to perform its specialized function - the thin layer maintains device complexity while the thick layer provides bonding pad strength
Solution Approach 2:
The bonding pad is constructed as a composite structure combining different metal materials with complementary properties. The AlCu layer provides electrical connectivity appropriate for image sensors, while the underlying tungsten or copper layer provides enhanced mechanical strength and peeling resistance, creating a composite bonding pad that satisfies both thin-layer and strength requirements
2Strength
If bonding pad size is increased to improve strength, then the bonding pad can withstand physical contact, but the overall feature size increases which contradicts the desire for smaller features
Solution Approach 1:
Instead of increasing the lateral area of the bonding pad, the solution extends vertically by adding a thicker underlying metal layer. This dimensional transition from 2D area expansion to 3D thickness enhancement provides the necessary strength and peeling resistance while maintaining the original small footprint of the bonding pad on the chip surface
3Length of moving object
If thin metal layers are used, then geometry size is decreased, but the bonding pads cannot withstand wire bonding or probing due to insufficient strength
Solution Approach 1:
A thick underlying metal layer is formed in advance beneath the thin AlCu bonding pad layer during the fabrication process. This preliminary structural reinforcement is established before wire bonding or probing operations, ensuring that the bonding pad has sufficient strength to withstand these subsequent mechanical operations despite the thinness of the visible metal layer
Data Source
AI summary
An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.