Bilayer Etch Stop Layer for Low-Capacitance Interconnects
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Solution Overview
Problem
The increasing complexity of semiconductor manufacturing processes due to shrinking device dimensions has led to higher parasitic capacitance and dynamic power loss in interconnect structures, particularly in back-end-of-line (BEOL) interconnects, where conventional etch stop layers with higher dielectric constants contribute to this issue.
Innovation Solution
A method is introduced to form an etch stop layer (ESL) structure comprising a low-density, low-dielectric-constant dielectric layer glued to a high-density dielectric layer with a glue layer, which reduces parasitic capacitance and serves as a hermetic moisture barrier, using oxygen-free materials to avoid oxidation concerns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etch stop layers with higher dielectric constants are used, then etch resistance is improved, but parasitic capacitance increases
Solution Approach 1:
The etch stop layer is segmented into a multi-layer structure comprising a first etch stop layer with higher dielectric constant and a second etch stop layer with lower dielectric constant. This segmentation allows different portions of the etch stop layer to perform different functions: the first layer provides etch resistance while the second layer reduces parasitic capacitance, thereby resolving the contradiction between etch resistance and capacitance reduction.
Solution Approach 2:
Different regions of the etch stop layer structure are assigned different dielectric constant properties. The first etch stop layer (closer to the substrate) has a higher dielectric constant for etch resistance, while the second etch stop layer (closer to the upper interconnect) has a lower dielectric constant for capacitance reduction. This local differentiation of material properties enables simultaneous achievement of both etch resistance and low capacitance.
2Productivity
If device dimensions are scaled down, then production efficiency is improved, but manufacturing process complexity increases
Solution Approach 1:
The etch stop layer is divided into multiple sub-layers with different material compositions and dielectric constants. This segmentation enables tailored optimization for specific etching conditions and interconnect requirements, allowing the manufacturing process to maintain control and efficiency even as device dimensions scale down and complexity increases.
Solution Approach 2:
The etch stop layer employs composite material structure combining different dielectric materials with distinct properties. This composite approach allows the structure to exhibit both high etch resistance (from the first layer) and low parasitic capacitance (from the second layer), providing a solution that maintains manufacturing efficiency while accommodating scaled-down device dimensions.
3Loss of energy
If low-density, low-dielectric-constant dielectric layer is used, then parasitic capacitance is reduced, but adhesion and moisture blocking capabilities deteriorate
Solution Approach 1:
The etch stop layer is segmented into two functional layers: the first layer with higher dielectric constant provides robust adhesion to the substrate and strong moisture blocking capability, while the second layer with lower dielectric constant provides the capacitance reduction benefit. This segmentation allows each layer to optimize for its specific function without compromising the other.
Solution Approach 2:
The etch stop layer structure uses composite materials where the first layer (higher dielectric constant) contributes adhesion and moisture blocking properties, while the second layer (lower dielectric constant) contributes to parasitic capacitance reduction. The composite structure synergistically combines these different material properties to achieve all three objectives simultaneously.
Data Source
AI summary
A method according to the present disclosure includes receiving a workpiece that includes a first conductive feature embedded in a first dielectric layer, selectively depositing a capping layer over the first conductive feature, depositing a first etch stop layer (ESL) over the capping layer, depositing a glue layer over the first ESL, depositing a second ESL over the glue layer, depositing a second dielectric layer over the second ESL, forming an opening through the second dielectric layer, the second ESL, the glue layer, and the first ESL to expose the capping layer, and forming a second conductive feature in the opening. A density of the second ESL is greater than a density of the first ESL.