Bilayer Memory Stacking With Shared Lines for Dense Low-Leakage Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing embedded memory technologies face challenges in achieving high density and low power consumption due to limitations in footprint area and leakage issues in frontend transistors, particularly in advanced technology nodes, which are exacerbated by the need for tall capacitors with small footprints and proximity to logic transistors.
Innovation Solution
Implementing bilayer memory stacking with shared lines between bottom and top memory layers in the backend of the IC device, using TFTs or layer transfer to move access transistors to the BEOL layer, allowing capacitors to be in upper metal layers with thicker interlayer dielectric and larger pitch, and enabling stacked memory arrays with shared lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory arrays are stacked in multiple layers with shared lines, then memory cell density increases or footprint area decreases, but leakage current from access transistors increases
Solution Approach 1:
The patent transitions from planar 2D memory organization to 3D stacked memory layers. Multiple memory arrays are stacked vertically with shared bitlines and wordlines, increasing memory density without proportionally increasing leakage. The three-dimensional stacking allows efficient use of shared interconnects across layers, reducing overall transistor count and leakage compared to duplicating full memory arrays in each layer.
Solution Approach 2:
The patent implements shared bitlines and wordlines that serve multiple memory arrays across different stacked layers. A single bitline or wordline can simultaneously access memory cells in multiple layers, reducing the total number of interconnects needed and minimizing leakage current while maintaining high memory density.
2Reliability
If capacitors are placed in upper metal layers with thicker interlayer dielectric, then manufacturing precision and reliability improve, but area occupied by each capacitor increases
Solution Approach 1:
The patent places capacitors in upper metal layers (e.g., M3, M4) with thicker interlayer dielectric materials. This vertical positioning in higher dimensions provides better manufacturing control and reliability for data retention while the shared line architecture compensates for the increased capacitor footprint by reducing overall memory array area requirements.
Solution Approach 2:
The patent combines multiple memory arrays into stacked layers that share common bitlines and wordlines. This merging allows the increased capacitor area in upper layers to be offset by the reduced interconnect area, as shared lines serve multiple arrays simultaneously, maintaining overall area efficiency.
3Loss of energy
If access transistors are moved to BEOL layer using TFT or layer transfer, then leakage is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts access transistors from the FEOL logic layer and relocates them to the BEOL memory layer using TFT (thin-film transistor) technology or layer transfer techniques. This separation removes leakage-prone access transistors from the high-performance FEOL, reducing overall leakage while confining BEOL operations to memory-specific processes.
Solution Approach 2:
The patent segments the manufacturing process into distinct FEOL and BEOL phases, with access transistors fabricated separately in the BEOL using TFT or layer transfer. This segmentation allows optimization of each layer for its specific function: FEOL for high-performance logic and BEOL for low-leakage memory access, reducing total device complexity through specialized processing.
Data Source
AI summary
IC devices implementing bilayer stacking with lines shared between bottom and top memory layers, and associated systems and methods, are disclosed. An example IC device includes a support structure, a front end of line (FEOL) layer and a back end of line (BEOL) layer. The BEOL layer includes a first memory cell in a first layer over the support structure, an electrically conductive line in a second layer, above the first layer, and a second memory cell in a third layer, above the second layer. The line could be one of a wordline, a bitline, or a plateline that is shared between the first and second memory cells. In particular, bilayer stacking line sharing is such that only one line is provided as a line to be shared between one or more of the memory cells of the first layer and one or more memory cells of the third layer.